AIS1120SX Datasheet, PDF (12/58 Pages) STMicroelectronics – Embedded self-test

Block diagrams and pin description
AIS1120SX / AIS2120SX
1.1.6
1.1.7
Signal compensation
On-chip EEPROM bits are used to compensate sensitivity error and offset error.
Linear interpolation
The device features an L-to-1 linear data interpolation computed from the present and the
previous samples. L depends on the cut-off frequency selected:
Interpolation factor:
– L = 16 if FIR_BW_SEL[1:0] = "00" or “11”
– L = 8 if FIR_BW_SEL[1:0] = "01"
– L = 4 if FIR_BW_SEL[1:0] = "10"
The data interpolation helps reduce sample jitter. The digital result will have a latency of one
sample time before being sent to the SPI bus.
The maximum jitter will be 62.5 s/16 = 3.9 s.
Figure 8 shows an interpolation example.
Figure 8. 8-to-1 interpolation timing
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