TS4855_04 Datasheet, PDF (21/27 Pages) STMicroelectronics – LOUDSPEAKER & HEADSET DRIVER WITH VOLUME CONTROL

Application Information
TS4855
The following graph shows an example of the
previous formula, with Vcc set to +5 V,
R_{load speaker} set to 8 Ω, and R_{load headphone} se to
16 Ω.
Figure 56: Example of total power dissipation
vs. speaker and headphone output power
1.2
1.0
0.8
0.6
0.4
0.2
0.0
0.0
Vcc=5V
THD+N<1%
Tamb=25°C
0.2 0.4 0.6 0.8 1.0
Speaker Ouput Power (W)
1.2
0 ⁵⁰_H¹_e⁰_a¹d^0p5_Ph²⁰_oo⁰_wn^{20eer5O(0mutWpu)t}
6.3 Low frequency response
In low frequency region, the effect of Cin starts.
Cin with Zin forms a high pass filter with a -3 dB
cut off frequency.
F_CL
=
2
1
π Zin Cin
(Hz )
Zin is the input impedance of the corresponding
input:
• 20 kΩ for Phone In IHF input
• 50 kΩ for the 3 other inputs
Note:
For all inputs, the impedance value remains
constant for all gain settings. This means that
the lower cut-off frequency doesn’t change with
gain setting. Note also that 20 kΩ and 50 kΩ are
typical values and there are tolerances around
these values (see Electrical Characteristics on
page 6).
In Figures 39 to 41, you could easily establish the
Cin value for a -3 dB cut-off frequency required.
6.4 Decoupling of the circuit
Two capacitors are needed to bypass properly the
TS4855, a power supply bypass capacitor Cs and
a bias voltage bypass capacitor Cb.
Cs has especially an influence on the THD+N in
high frequency (above 7 kHz) and indirectly on
the power supply disturbances.
With 1 µF, you could expect similar THD+N
performances like shown in the datasheet.
If Cs is lower than 1 µF, THD+N increases in high
frequency and disturbances on the power supply
rail are less filtered.
To the contrary, if Cs is higher than 1 µF, those
disturbances on the power supply rail are more
filtered.
Cb has an influence on THD+N in lower
frequency, but its value is critical on the final result
of PSRR with input grounded in lower frequency:
• If Cb is lower than 1 µF, THD+N increases at
lower frequencies and the PSRR worsens
upwards.
• If Cb is higher than 1 µF, the benefit on
THD+N and PSRR in the lower frequency
range is small.
6.5 Startup time
When the TS4855 is controlled to switch from the
full standby mode (output mode 0) to another
output mode, a delay is necessary to stabilize the
DC bias. This delay depends on the Cb value and
can be calculated by the following formulas.
Typical startup time = 0.0175 x Cb (s)
Max. startup time = 0.025 x Cb (s)
(Cb is in µF in these formulas)
These formulas assume that the Cb voltage is
equal to 0 V. If the Cb voltage is not equal to 0V,
the startup time will be always lower.
The startup time is the delay between the
negative edge of Enable input (see SPI Operation
Description on page 3) and the power ON of the
output amplifiers.
Note:
When the TS4855 is set in full standby mode,
Cb is discharged through an internal switch.
The time to reach 0 V of Cb voltage with 1µF is
about 1ms.
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