TDA7502_06 Datasheet, PDF (19/25 Pages) STMicroelectronics – In-car remote amplifier DSP

TDA7502
Functional description
6.3.5
6.3.6
6.3.7
Essentially this consists of a routine that is called when the DSP comes out of reset. There
are four different boot modes supported by the boot ROM. The first mode loads the
application program via SPI interface where Casper’s SPI is in master mode. The second
boot mode enables the debug port and waits. The third and fourth modes load the
application program via the I²C interface, one with Casper’s I²C Interface configured in slave
mode and the other in master mode. Which boot mode to enter is configured by sampling
the states of the GPIO4 and GPIO3 pins at reset as shown in the table below.
Table 15. Casper IC boot modes
Modes
Description
0-SPI Master load PRAM, XRAM and YRAM from SPI
1-Debug
2-I²C Master
3-I²C Slave
enable Debug Port
load PRAM, XRAM and YRAM from I²C
oad PRAM, XRAM and YRAM from I²C
GPIO3
0
0
1
1
GPIO4
0
1
0
1
Serial audio interface (SAI)
The SAI is used to deliver digital audio to the DSPs from an external source. Once
processed by the DSPs, it can be returned through this interface. The features of the SAI
are listed below.
● Three synchronized stereo data transmission lines
● Three synchronized stereo data reception lines
● Master/Slave operating modes
● Transmit and receive interrupt logic triggers on left/right data pairs
● Receive and transmit data registers have two locations to hold left and right data.
Serial peripheral interface
A serial interface allows to receive commands and data over the LAN. During an SPI
transfer, data is transmitted and received simultaneously. Both master and slave modes are
supported.
In master mode the SPI supports combination of CPOL =0/1 and CPHA =0 only, while in
slave mode all the 4 possible combinations of CPOL and CPHA are supported. See Figure
9.
A serial clock line synchronizes shifting and sampling of the information on the two serial
data lines. A slave select line allows individual selection of a slave SPI device.
When an SPI transfer occurs an 8-bit word is shifted out one data pin while another 8-bit
character is simultaneously shifted in a second data pin.The central element in the SPI
system is the shift register and the read data buffer. The system is single buffered in the
transfer direction and double buffered in the receive direction.
I²C interface
The inter integrated circuit bus is a single bidirectional two-wire bus used for efficient inter IC
control. All I²C bus compatible devices incorporate an on-chip interface which allows them
communicate directly with each other via the I²C bus.
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