TDA7502_06 Datasheet, PDF (16/25 Pages) STMicroelectronics – In-car remote amplifier DSP

I2C timing
5
I²C timing
TDA7502
Figure 15. Definition of timing for the I²C bus.
SDA
t_BUF
t_LOW
t_SU:STA
t_F
SCL
t_HD:STA
t_R
t_HD:DAT
t_HIGH
t_SU:DAT
t_HD:STA
t_SU:STO
D02AU1371
Table 14. Definitions
Symbol
Parameter
Test condition
Standard
mode
I²C bus
Fast mode
I²C bus
Unit
F_SCL
t_BUF
SCLl clock frequency
Bus free between a STOP and Start
Condition
Hold time (repeated) START condition.
t_HD:STA After this period, the first clock pulse is
generated
t_LOW LOW period of the SCL clock
t_HIGH HIGH period of the SCL clock
t_SU:STA Set-up time for a repeated start condition
t_HD:DAT DATA hold time
t_R Rise time of both SDA and SCL signals Cb in pF
t_F Fall time of both SDA and SCL signals Cb in pF
t_SU;STO Set-up time for STOP condition
t_SU:DAT Data set-up time
C_b Capacitive load for each bus line
Min. Max.
0 100
4.7
–
Min.
0
1.3
Max.
400 kHz
–
μs
4.0
–
0.6
–
μs
4.7
–
1.3
–
μs
4.0
–
0.6
–
μs
4.7
–
0.6
–
μs
0
–
0
0.9 μs
– 1000 20+0.1C_b 300 ns
–
300 20+0.1C_b 300
ns
4
–
0.6
–
μs
250 --
--
100 ns
– 400
–
400 pF
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