M24C64-FDW5TP Datasheet, PDF (19/45 Pages) STMicroelectronics – 64-Kbit serial I²C bus EEPROM

M24C64-W M24C64-R M24C64-F
5.2
Read operations
Read operations are performed independently of the state of the Write Control (WC) signal.
After the successful completion of a Read operation, the device internal address counter is
incremented by one, to point to the next byte address.
For the Read instructions, after each byte read (data out), the device waits for an
acknowledgment (data in) during the 9th bit time. If the bus master does not acknowledge
during this 9th time, the device terminates the data transfer and switches to its Standby
mode.
Current
Address
Read
Figure 12. Read mode sequences
ACK
NO ACK
Dev sel
Data out
R/W
Random
Address
Read
ACK
ACK
ACK
ACK
NO ACK
Dev sel *
Byte addr
Byte addr
Dev sel *
Data out
R/W
R/W
Sequential
Current
Read
Sequention
Random
Read
ACK
ACK
Dev sel
Data out 1
R/W
ACK
NO ACK
Data out N
ACK
ACK
ACK
ACK
ACK
Dev sel *
Byte addr
Byte addr
Dev sel *
Data out1
R/W
R/W
ACK
NO ACK
Data out N
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