M24C64-FDW5TP Datasheet, PDF (16/45 Pages) STMicroelectronics – 64-Kbit serial I²C bus EEPROM

Instructions
M24C64-W M24C64-R M24C64-F
5.1.2
Page Write
The Page Write mode allows up to 32 bytes to be written in a single Write cycle, provided
that they are all located in the same page in the memory: that is, the most significant
memory address bits, A15/A5, are the same. If more bytes are sent than will fit up to the end
of the page, a “roll-over” occurs, i.e. the bytes exceeding the page end are written on the
same page, from location 0.
The bus master sends from 1 to 32 bytes of data, each of which is acknowledged by the
device if Write Control (WC) is low. If Write Control (WC) is high, the contents of the
addressed memory location are not modified, and each data byte is followed by a NoAck, as
shown in Figure 10. After each transferred byte, the internal page address counter is
incremented.
The transfer is terminated by the bus master generating a Stop condition.
Figure 10. Write mode sequences with WC = 1 (data write inhibited)
7#
"YTE7RITE
!#+
!#+
!#+
./!#+
$EVSEL
"YTEADDR
"YTEADDR
$ATAIN
27
7#
0AGE7RITE
!#+
!#+
!#+
./!#+
$EVSEL
"YTEADDR
"YTEADDR
$ATAIN
$ATAIN
27
7#CONTgD
0AGE7RITECONTgD
./!#+
./!#+
$ATAIN.
!)D
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