STM32F745IE Datasheet, PDF (189/227 Pages) STMicroelectronics – Up to 168 I/O ports with interrupt capability

STM32F745xx STM32F746xx
Electrical characteristics
5.3.28
Symbol
Table 105. LPSDR SDRAM write timings⁽¹⁾
Parameter
Min
Max
t_w(SDCLK)
FMC_SDCLK period
t_{d(SDCLKL _Data})
Data output valid time
t_{h(SDCLKL _Data)}
Data output hold time
t_{d(SDCLKL_Add)}
Address valid time
t_{d(SDCLKL-SDNWE)}
SDNWE valid time
t_{h(SDCLKL-SDNWE)}
SDNWE hold time
t_{d(SDCLKL- SDNE)}
Chip select valid time
t_{h(SDCLKL- SDNE)}
Chip select hold time
t_{d(SDCLKL-SDNRAS)}
SDNRAS valid time
t_{h(SDCLKL-SDNRAS)}
SDNRAS hold time
t_{d(SDCLKL-SDNCAS)}
SDNCAS valid time
t_{d(SDCLKL-SDNCAS)}
SDNCAS hold time
1. Guaranteed by characterization results.
2T_HCLK−0.5
-
0
-
-
0
-
0
-
0
-
0
2T_HCLK+0.5
4
-
3.5
0.5
-
0.5
-
0.5
-
0.5
-
Unit
ns
Quad-SPI interface characteristics
Unless otherwise specified, the parameters given in Table 106 and Table 107 for Quad-SPI
are derived from tests performed under the ambient temperature, f_AHB frequency and V_DD
supply voltage conditions summarized in Table 17: General operating conditions, with the
following configuration:
• Output speed is set to OSPEEDRy[1:0] = 11
• Capacitive load C = 20 pF
• Measurement points are done at CMOS levels: 0.5 ₓ V_DD
Refer to Section 5.3.17: I/O port characteristics for more details on the input/output alternate
function characteristics.
Symbol
Fck1/t(CK)
Table 106. Quad-SPI characteristics in SDR mode⁽¹⁾
Parameter
Conditions
Min
Typ
Max Unit
Quad-SPI clock
2.7 V≤V_DD<3.6 V
CL=20 pF
-
frequency
1.71 V<V_DD<3.6 V
CL=15 pF
-
-
108
MHz
-
100
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