STM32F745IE Datasheet, PDF (100/227 Pages) STMicroelectronics – Up to 168 I/O ports with interrupt capability

Electrical characteristics
STM32F745xx STM32F746xx
6. _{VIt D}is_DAreccaonmbmeetnodleerdatteodpdouwreinrgVp_{DoDwaenrd-uVpDaDnAdfrpoomwethr-edosawmneopseoruartcioen. .A} maximum difference of 300 mV between V_DD and
7. The over-drive mode is not supported when the internal regulator is OFF.
8. To sustain a voltage higher than VDD+0.3, the internal Pull-up and Pull-Down resistors must be disabled
9. If T_A is lower, higher P_D values are allowed as long as T_J does not exceed T_Jmax.
10. In low power dissipation state, T_A can be extended to this range as long as T_J does not exceed T_Jmax.
Table 18. Limitations depending on the operating power supply range
Operating
power supply
range
ADC operation
Maximum Flash
memory access
frequency with
no wait states
(f_Flashmax)
Maximum HCLK
frequency vs Flash
memory wait states
(1)(2)
I/O operation
Possible Flash
memory
operations
V_D2D.1=V1.(7₃₎ to
Conversion time
up to 1.2 Msps
20 MHz
180 MHz with 8 wait
states and over-drive
OFF
No I/O
compensation
8-bit erase and
program
operations only
V_DD = 2.1 to Conversion time
2.4 V
up to 1.2 Msps
22 MHz
216 MHz with 9 wait
states and over-drive
ON
No I/O
compensation
16-bit erase and
program
operations
V_DD = 2.4 to Conversion time
2.7 V
up to 2.4 Msps
24 MHz
216 MHz with 8 wait
states and over-drive
ON
I/O compensation
works
16-bit erase and
program
operations
V_DD =
3.6
2.7
V⁽⁴⁾
to
Conversion time
up to 2.4 Msps
30 MHz
216 MHz with 7 wait
states and over-drive
ON
I/O compensation
works
32-bit erase and
program
operations
1. Applicable only when the code is executed from Flash memory. When the code is executed from RAM, no wait state is
required.
2. Thanks to the ART accelerator on ITCM interface and L1-cache on AXI interface, the number of wait states given here
does not impact the execution speed from Flash memory since the ART accelerator or L1-cache allows to achieve a
performance equivalent to 0-wait state program execution.
3. _IV_nDteDr/_nV_aDlDrAesm_ei_tn_Oim_Fu_Fm). value of 1.7 V is obtained with the use of an external power supply supervisor (refer to Section 2.17.2:
4. The voltage range for USB full speed PHYs can drop down to 2.7 V. However the electrical characteristics of D- and D+
pins will be degraded between 2.7 and 3 V.
5.3.2
VCAP1/VCAP2 external capacitor
Stabilization for the main regulator is achieved by connecting an external capacitor C_EXT to
the VCAP1/VCAP2 pins. C_EXT is specified in Table 19.
Figure 24. External capacitor C_EXT
&
(65
1. Legend: ESR is the equivalent series resistance.
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