STM32F745IE Datasheet, PDF (181/227 Pages) STMicroelectronics – Up to 168 I/O ports with interrupt capability

STM32F745xx STM32F746xx
Electrical characteristics
Figure 64. Synchronous non-multiplexed NOR/PSRAM read timings
TW#,+
&-#?#,+
TD#,+, .%X,
&-#?.%X
TD#,+, .!$6,
TW#,+
$ATALATENCY
TD#,+, .!$6(
TD#,+( .%X(
&-#?.!$6
&-#?!;=
TD#,+, !6
TD#,+( !)6
TD#,+, ./%,
TD#,+( ./%(
&-#?./%
&-#?$;=
&-#?.7!)4
7!)4#&'B
7!)40/,B
&-#?.7!)4
7!)4#&'B
7!)40/,B
TSU$6 #,+(
TSU.7!)46 #,+(
TH#,+( $6
TSU$6 #,+(
$
$
TH#,+( $6
TH#,+( .7!)46
TSU.7!)46 #,+(
T _{H#,+( .7!)46}
TSU.7!)46 #,+(
TH#,+( .7!)46
-36
Table 98. Synchronous non-multiplexed NOR/PSRAM read timings⁽¹⁾
Symbol
Parameter
Min
Max
t_w(CLK)
FMC_CLK period
2T_HCLK−1
-
t_(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2)
-
2.5
t_d(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0…2)
T_HCLK+0.5
-
t_{d(CLKL-NADVL)} FMC_CLK low to FMC_NADV low
-
0
t_{d(CLKL-NADVH)} FMC_CLK low to FMC_NADV high
0
-
t_d(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=16…25)
-
2.5
t_d(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x=16…25)
T_HCLK
-
t_d(CLKL-NOEL) FMC_CLK low to FMC_NOE low
-
2
t_d(CLKH-NOEH) FMC_CLK high to FMC_NOE high
T_HCLK+0.5
-
t_su(DV-CLKH) FMC_D[15:0] valid data before FMC_CLK high
1.5
-
t_h(CLKH-DV) FMC_D[15:0] valid data after FMC_CLK high
1
-
t_(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high
2
-
t_{h(CLKH-NWAIT)} FMC_NWAIT valid after FMC_CLK high
3.5
-
Unit
ns
DocID027590 Rev 4
181/227
195