TDA7522 Datasheet, PDF (18/23 Pages) STMicroelectronics – Digital Servo & Decoder

TDA7522
Subcode processing consists of CRC parity check and Subcode decoder.
There are 2 different buffers for Q Subcode data and for R-W subcode data.
Q subcode data is transferred to ST7 every symbol by interruption and the result of CRC is also reported
to ST7. R-W subcode data especially for CD-Text data through program area is arranged to 8bit format
from 6bit of R to W, then ST7 stores max. 144byte (8pack data) as a FIFO to allow the tolerant of reading
timing from external MPU for display and also 1block CD-Text data from TOC area can be transferred to
ST7 4Kbyte CD-Text RAM.
5.5 CIRC (Error correction)
CIRC (Cross Interleaving Read Solomon code) consists of 2 following blocks;
– Memory control for
M1: The FIFO memory to absorb Jitter of input signals
M2: The De-interleaving memory
M1 FIFO memory compensates the speed deviations of the spindle motor and M2 is used for the de-in-
terleaving between the C1 and C2 decoder. The size of the RAM is 16Kbit and the width is 9bit. Each 9
bit word consists of 8 bit data (symbols) and 1 bit validity flag.
– Error Correction
This block represents a Reed Solomon decoder which forms a CIRC decoder for CD in conjunction with
CIRC RAM.
There are two decoder circuits:
– the first C1 decoder can correct up two random errors in a 32-byte frame, marking uncorrectable errors
as erasures
– the second C2 decoder can correct up to four erasures in a 28 byte frame.
5.6 Shock proof memory control
This is a shock proof memory controller which absorbs the interruption due to the shocks.
Namely, it controls external DRAM in order to store the audio data into RAM earlier than the reading.
Therefore during shocks the data of the RAM can be played without any interruption of the data.
The controller handles the data from Acquisition and output into RAM&Timing block. It means the stored
data into RAM is ADAT[7-0] before error correction. That is why complete 32 Symbols / Frame including
CRC must be stored into RAM. It allows the use of Audio RAM (ARAM) with defects which is much cheap-
er than standard DRAM.
The difference between the classical shock proof memory controller like SONY and this new controller is
that ARAM use with defects, the location of the memory and the controller, and also how to fill the data
into RAM earlier than reading. In case of our controller, CLV servo (Disk motor controller) varies the disk
speed in order to store certain amount of data into RAM earlier than the reading. Then as long as certain
amount of data is kept in the RAM in advance, the disk speed is controlled with single speed (normal
speed) operation, not always double speed operation like classical solution.
Mainly the shock proof memory controller consists of 3 controllers.
One is the writing pointer controller which controls the memory address for writing data, the another is the
reading pointer controller which controls the memory address for reading data, the other is timing arbitra-
tion between the reading and writing procedure of the data and address.
The output data from the memory is delivered always with fixed data rate without jitters, however the in-
coming data is not delivered with fixed rate because of the jitters from the disk and the varied speed of the
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