TDA7522 Datasheet, PDF (17/23 Pages) STMicroelectronics – Digital Servo & Decoder

TDA7522
– Some Digital filters for Adjustments by ST7
– Sine wave generator for reference of internal adjustment and DAC measurement
– Filter for Shock detector
– 8 times high end Audio Over sampling
– De-emphasis filter
– Audio attenuation, mute and balance
– Internal Signal observation feature for user measurement
– Soft mute and data concealment
– Audio peak detection
– Focus error, Tracking error generation
– Equalization of Tracking Zero Cross signal
– Sound Vector Enhancement filter.
5.3 DATA Acquisition
The digital HF signal is input to an digital equalizer to improved the bit detection. Different equalizer coef-
ficients are selectable by MPU.
The digital data slicer is implemented and the internal slice level is calculated by using a leakage free in-
tegrator which is subtracted from HF. The properly levelled EFM is delivered to the edge detector and a
digital bit clock PLL. On this stage, no analog VCO is necessary to obtain bit clock but DTO (Discrete Time
Oscillator) is used.
The Digital PLL block consists of following functions;
– Adaptive HF Equalization
– HF HPF for disturbance rejection
– Digital Data slicer
– Linear interpolation for Phase error measurement
– Run length detection for Frequency error measurement
– Frequency & Phase Control loop
– DTO block
– EFM bit generation.
The serial bit stream signal from the phase detected is sent to a shift register block, which includes differ-
ent functions as follows;
– serial to parallel conversion
– detection of frame sync pattern
– protection and insertion of frame sync
– bit clock counter (588 bits per frame)
– synchronization and sync window logic
– 14 to 8 bit demodulation
– subcode extraction.
5.4 Subcode extraction
This block receives the subcode data stream and the related S0/S1 synchronization information from Ac-
quisition part.
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