STCF04 Datasheet, PDF (18/43 Pages) STMicroelectronics – Cell phones and smartphones

Detailed description
STCF04
Data transmission from the main microprocessor to the STCF04 and vice versa takes place
through the 2 I²C bus interface wires, consisting of the two lines SDA and SCL (pull-up
resistors to a positive supply voltage must be externally connected).
8.1.8
Figure 5.
Data validity
As shown in Figure 5, the data on the SDA line must be stable during the high period of the
clock. The HIGH and LOW state of the data line can only change when the clock signal on
the SCL line is LOW.
Data validity on the I²C bus
8.1.9
CS11340
START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. As shown in Figure 6, a
START condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The STOP
condition is a LOW to HIGH transition of the SDA line while SCL is HIGH. A STOP condition
must be sent before each START condition.
Figure 6. Timing diagram on I²C bus
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Doc ID 022927 Rev 3