H3LIS331DL Datasheet, PDF (18/38 Pages) STMicroelectronics – MEMS motion sensor: low-power high-g 3-axis digital accelerometer

Digital interfaces
H3LIS331DL
5.1.1
I²C operation
The transaction on the bus is started through a START (ST) signal. A START condition is
defined as a high-to-low transition on the data line while the SCL line is held high. After this
has been transmitted by the master, the bus is considered busy. The next byte of data
transmitted after the START condition contains the address of the slave in the first 7 bits and
the eighth bit tells whether the master is receiving data from the slave or transmitting data to
the slave. When an address is sent, each device in the system compares the first seven bits
after a START condition with its address. If they match, the device considers itself
addressed by the master.
The slave address (SAD) associated to the H3LIS331DL is 001100xb. The SDO/SA0 pad
can be used to modify the less significant bit of the device address. If the SA0 pad is
connected to the voltage supply, LSB is ‘1’ (address 0011001b) or else, if the SA0 pad is
connected to ground, the LSB value is ‘0’ (address 0011000b). This solution allows the
connection and addressing of two different accelerometers to the same I²C lines.
Data transfer with acknowledge is mandatory. The transmitter must release the SDA line
during the acknowledge pulse. The receiver must then pull the data line low so that it
remains stable low during the high period of the acknowledge clock pulse. A receiver which
has been addressed is obliged to generate an acknowledge after each byte of data
received.
The I²C embedded inside the H3LIS331DL behaves like a slave device and the following
protocol must be adhered to. After the START condition (ST) a slave address is sent, once a
slave acknowledge (SAK) has been returned, an 8-bit sub-address (SUB) is transmitted: the
7 LSB represent the actual register address while the MSB enables address auto increment.
If the MSB of the SUB field is ‘1’, the SUB (register address) is automatically increased to
allow multiple data read/write.
The slave address is completed with a Read/Write bit. If the bit is ‘1’ (read), a repeated
START (SR) condition must be issued after the two sub-address bytes; if the bit is ‘0’ (write),
the master transmits to the slave with the direction unchanged. Table 10 explains how the
SAD+Read/Write bit pattern is composed, listing all the possible configurations.
Command
Read
Write
Read
Write
Table 10. SAD+Read/Write patterns
SAD[6:1]
SAD[0] = SA0
R/W
001100
0
1
001100
0
0
001100
1
1
001100
1
0
SAD+R/W
00110001 (31h)
00110000 (30h)
00110011 (33h)
00110010 (32h)
Table 11. Transfer when master is writing one byte to slave
Master
ST
SAD + W
SUB
DATA
SP
Slave
SAK
SAK
SAK
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