ST10F273Z4 Datasheet, PDF (176/188 Pages) STMicroelectronics – 16-bit MCU with 512 Kbyte Flash memory and 36 Kbyte RAM

Electrical characteristics
Figure 60. SSC slave timing
t₃₁₀
t₃₁₁ t₃₁₂
1)
SCLK
t₃₁₄
t₃₁₅
t₃₁₅
2)
t₃₁₃
t₃₁₆
MRST
1st out bit 2nd out bit
t₃₁₇ t₃₁₈
MTSR
1st in bit
2nd in bit
ST10F273Z4
t₃₁₅
Last out bit
t₃₁₇ t₃₁₈
Last in bit
1. The phase and polarity of shift and latch edge of SCLK is programmable. This figure uses the leading clock
edge as shift edge (drawn in bold), with latch on trailing edge (SSCPH = 0b), Idle clock line is low, leading
clock edge is low-to-high transition (SSCPO = 0b).
2. The bit timing is repeated for all bits to be transmitted or received.
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