ST10F273Z4 Datasheet, PDF (175/188 Pages) STMicroelectronics – 16-bit MCU with 512 Kbyte Flash memory and 36 Kbyte RAM

ST10F273Z4
Electrical characteristics
Slave mode
V_DD = 5V ±10%, V_SS = 0V, T_A = -40 °C to +125 °C, C_L = 50 pF
Table 83.
Symbol
SSC slave mode timings
Parameter
Max. Baud rate
6.6 MBd ⁽¹⁾
@F_CPU = 40 MHz
(<SSCBR> = 0002h)
Variable Baudrate
(<SSCBR> = 0001h -
FFFFh)
Unit
Min.
Max.
Min.
Max.
t₃₁₀ SR SSC clock cycle time ⁽²⁾
t₃₁₁ SR SSC clock high time
t₃₁₂ SR SSC clock low time
t₃₁₃ SR SSC clock rise time
t₃₁₄ SR SSC clock fall time
t₃₁₅
CC
Write data valid after shift
edge
150
150
8TCL 262144 TCL
63
–
t₃₁₀ / 2 – 12
–
63
–
t₃₁₀ / 2 – 12
–
–
10
–
10
–
10
–
10
–
55
–
2TCL + 30
t₃₁₆
CC
Write data hold after shift
edge
0
–
0
–
Read data setup time before
t_317p SR latch edge, phase error
62
detection on (SSCPEN = 1)
ns
–
4TCL + 12
–
Read data hold time after
t_318p SR latch edge, phase error
87
detection on (SSCPEN = 1)
–
6TCL + 12
–
Read data setup time before
t₃₁₇ SR latch edge, phase error
6
–
6
–
detection off (SSCPEN = 0)
Read data hold time after
t₃₁₈ SR latch edge, phase error
31
detection off (SSCPEN = 0)
–
2TCL + 6
–
1. Maximum Baudrate is in reality 8Mbaud, that can be reached with 64 MHz CPU clock and <SSCBR> set to
‘3h’, or with 48 MHz CPU clock and <SSCBR> set to ‘2h’. When 40 MHz CPU clock is used the maximum
baudrate cannot be higher than 6.6Mbaud (<SSCBR> = ‘2h’) due to the limited granularity of <SSCBR>.
Value ‘1h’ for <SSCBR> may be used only with CPU clock lower than 32 MHz (after checking that resulting
timings are suitable for the master).
2. Formula for SSC Clock Cycle time: t₃₁₀ = 4 TCL * (<SSCBR> + 1)
Where <SSCBR> represents the content of the SSC Baudrate register, taken as unsigned 16-bit integer.
Minimum limit allowed for t₃₁₀ is 125ns (corresponding to 8Mbaud).
175/188