STM32L452XX Datasheet, PDF (174/210 Pages) STMicroelectronics – Ultra-low-power with FlexPowerControl

Electrical characteristics
STM32L452xx
Table 90. IWDG min/max timeout period at 32 kHz (LSI)⁽¹⁾
Prescaler divider PR[2:0] bits
Min timeout RL[11:0]=
0x000
Max timeout RL[11:0]=
0xFFF
Unit
/4
0
0.125
512
/8
1
/16
2
/32
3
/64
4
/128
5
/256
6 or 7
0.250
0.500
1.0
2.0
4.0
8.0
1024
2048
4096
ms
8192
16384
32768
1. The exact timings still depend on the phasing of the APB interface clock versus the LSI clock so that there
is always a full RC period of uncertainty.
Table 91. WWDG min/max timeout value at 80 MHz (PCLK)
Prescaler
WDGTB
Min timeout value
Max timeout value
Unit
1
0
0.0512
3.2768
2
1
4
2
0.1024
0.2048
6.5536
ms
13.1072
8
3
0.4096
26.2144
6.3.25
Communication interfaces characteristics
I²C interface characteristics
The I2C interface meets the timings requirements of the I²C-bus specification and user
manual rev. 03 for:
• Standard-mode (Sm): with a bit rate up to 100 kbit/s
• Fast-mode (Fm): with a bit rate up to 400 kbit/s
• Fast-mode Plus (Fm+): with a bit rate up to 1 Mbit/s.
The I2C timings requirements are guaranteed by design when the I2C peripheral is properly
configured (refer to RM0394 reference manual).
The SDA and SCL I/O requirements are met with the following restrictions: the SDA and
SCL I/O pins are not “true” open-drain. When configured as open-drain, the PMOS
connected between the I/O pin and V_DDIOx is disabled, but is still present. Only FT_f I/O pins
support Fm+ low level output current maximum requirement. Refer to Section 6.3.14: I/O
port characteristics for the I2C I/Os characteristics.
All I2C SDA and SCL I/Os embed an analog filter. Refer to the table below for the analog
filter characteristics:
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