EVALST7590-1 Datasheet, PDF (17/24 Pages) STMicroelectronics – Narrow-band OFDM power line networking PRIME compliant system-on-chip

ST7590
Figure 7. Power supply internal scheme
8-18V
External Supply
VCC
VSS
VCCA
3.3 or 5V
External Supply
VSSA
VDDIO
GND
VDD
VDD_PLL
VSSA
Analog front end (AFE)
LDO
POWER AMPLIFIER
AFE
DIGITAL INTERFACES
LDO
DIGITAL CORE
INTERNAL PLL
4.8
Clock management
The main clock source is an 8 MHz crystal connected to the internal oscillator through XIN
and XOUT pins. Both XIN and XOUT pins have a 32 pF integrated capacitor, in order to
drive a crystal having a load capacitance of 16 pF with no additional components.
Alternatively, an 8 MHz external clock can be directly supplied to XIN pin, leaving XOUT
floating.
A PLL internally connected to the output of the oscillator generates the internal clocks
needed by the digital part.
Doc ID 18349 Rev 1
17/24