ST10F271 Datasheet, PDF (166/173 Pages) STMicroelectronics – 16-bit MCU with 128 Kbyte Flash memory and 12 Kbyte RAM

Electrical characteristics
ST10F271
Figure 60. External bus arbitration (regaining the bus)
2)
CLKOUT
HOLD
t₆₁
t₆₂
HLDA
BREQ
CSx
(On P6.x)
Other
signals
t₆₂
t₆₂
t₆₃
1)
t₆₅
t₆₇
1. This is the last chance for BREQ to trigger the indicated regain-sequence. Even if BREQ is activated
earlier, the regain-sequence is initiated by HOLD going high. Please note that HOLD may also be
deactivated without the ST10F271 requesting the bus.
2. The next ST10F271 driven bus cycle may start here.
24.8.20 High-speed synchronous serial interface (SSC) timing
Master mode
V_DD = 5V ±10%, V_SS = 0V, T_A = -40 to +125°C, C_L = 50pF
Table 81. SSC master mode timings
Symbol
Parameter
Max. Baudrate 6.6MBd
(1)_{@FCPU = 40MHz}
(<SSCBR> = 0002h)
Variable Baudrate
(<SSCBR> = 0001h -
FFFFh)
Unit
t₃₀₀
t₃₀₁
t₃₀₂
t₃₀₃
t₃₀₄
t₃₀₅
t₃₀₆
t_307p
CC SSC clock cycle time⁽²⁾⁾
CC SSC clock high time
CC SSC clock low time
CC SSC clock rise time
CC SSC clock fall time
CC Write data valid after shift edge
CC Write data hold after shift edge⁽³⁾
Read data setup time before latch
SR edge, phase error detection on
(SSCPEN = 1)
min.
150
63
63
–
–
–
–2
37.5
max.
150
–
–
10
10
15
–
–
min.
max.
8TCL
262144 TCL ns
t₃₀₀ / 2 – 12
–
ns
t₃₀₀ / 2 – 12
–
ns
–
10
ns
–
10
ns
–
15
ns
–2
–
ns
2TCL + 12.5
–
ns
166/173