ST10F271 Datasheet, PDF (128/173 Pages) STMicroelectronics – 16-bit MCU with 128 Kbyte Flash memory and 12 Kbyte RAM

Electrical characteristics
ST10F271
Table 63. DC characteristics (continued)
Parameter
Symbol
Limit values
Unit
Test Condition
min.
max.
Port 6 inactive current (P6[4:0]) ^{(6) (7)}
Port 6 active current (P6[4:0]) ^{(6) (8)}
PORT0 configuration current ⁽⁶⁾
I_P6H
I_P6L
I_P0H ⁶⁾
I_P0L ⁷⁾
Pin Capacitance (Digital inputs / outputs) C_IO CC
Run Mode Power supply current ⁽⁹⁾
(Execution from Internal RAM)
I_CC1
Run Mode Power supply current ^{(1) (10)}
(Execution from Internal Flash)
I_CC2
Idle mode supply current ⁽¹¹⁾
I_ID
Power Down supply current ⁽¹²⁾
(RTC off, Oscillators off,
I_PD1
Main Voltage Regulator off)
–
–500
–
–100
–
–
–
–
–
–40
µA
–
µA
–10
µA
–
µA
10
pF
15 + 1.5
f_CPU
mA
15 + 1.5
f_CPU
mA
15 + 0.6
f_CPU
mA
200
µA
V_OUT = 2.4 V
V_OUT = 0.4V
V_IN = 2.0V
V_IN = 0.8V
(1) (6)
–
–
–
T_A = 25°C
Power Down supply current ⁽¹²⁾
(RTC on, Main Oscillator on,
I_PD2
Main Voltage Regulator off)
Power Down supply current ⁽¹²⁾
(RTC on, 32kHz Oscillator on,
I_PD3
Main Voltage Regulator off)
400
–
Typical
µA
Value
–
200
µA
T_A = 25°C
T_A = 25°C
Stand-by supply current ⁽¹²⁾
(RTC off, Oscillators off, V_DD off, V_STBY I_SB1
on)
–
120
µA
V_STBY = 5.5 V
T_A = T_J = 25°C
–
500
µA
V_STBY = 5.5 V
T_A = T_J = 125°C
Stand-by supply current ⁽¹²⁾
(RTC on, 32kHz Oscillator on,
I_SB2
main V_DD off, V_STBY on)
Stand-by supply current ^{(1) (12)}
(V_DD transient condition)
I_SB3
–
120
µA
V_STBY = 5.5 V
T_A = T_J = 125°C
–
500
µA
V_STBY = 5.5 V
T_A = T_J = 125°C
–
2.5
mA
–
1. Not 100% tested, guaranteed by design characterization.
2. This specification is not valid for outputs which are switched to open drain mode. In this case the respective output will float
and the voltage is imposed by the external circuitry.
3. Port 5 leakage values are granted for not selected A/D Converter channel. One channels is always selected (by default,
after reset, P5.0 is selected). For the selected channel the leakage value is similar to that of other port pins.
4. The leakage of P2.0 is higher than other pins due to the additional logic (pass gates active only in specific test modes)
implemented on input path. Pay attention to not stress P2.0 input pin with negative overload beyond the specified limits:
failures in Flash reading may occur (sense amplifier perturbation). Refer to next Figure 37: Port2 test mode structure for a
scheme of the input circuitry.
5. Overload conditions occur if the standard operating conditions are exceeded, i.e. the voltage on any pin exceeds the
specified range (i.e. V_OV > V_DD + 0.3 V or V_OV < –0.3 V). The absolute sum of input overload currents on all port pins may
not exceed 50mA. The supply voltage must remain within the specified limits.
6. This specification is only valid during Reset, or during Hold- or Adapt-mode. Port 6 pins are only affected, if they are used
for CS output and the open drain function is not enabled.
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