ST10F271 Datasheet, PDF (165/173 Pages) STMicroelectronics – 16-bit MCU with 128 Kbyte Flash memory and 12 Kbyte RAM

ST10F271
Electrical characteristics
Table 80. External bus arbitration timings
Symbol
Parameter
F_CPU = 40 MHz
TCL = 12.5 ns
min.
max.
Variable CPU Clock
1/2 TCL = 1 to 64MHz
min.
max.
t₆₁ SR
HOLD input setup time
to CLKOUT
18.5
t₆₂ CC
CLKOUT to HLDA high
or BREQ low delay
–
t₆₃ CC
CLKOUT to HLDA low
or BREQ high delay
–
t₆₄ CC
CSx release ¹⁾
–
t₆₅ CC
CSx drive
–4
t₆₆ CC
Other signals release ¹⁾
–
t₆₇ CC
Other signals drive
–4
1. Partially tested, guaranteed by design characterization.
–
12.5
12.5
20
15
20
15
18.5
–
–
–
–4
–
–4
–
ns
12.5
ns
12.5
ns
20
ns
15
ns
20
ns
15
ns
Figure 59. External bus arbitration (releasing the bus)
CLKOUT
t₆₁
HOLD
HLDA
BREQ
CSx
(P6.x)
Others
t₆₃
1)
t₆₂
2)
t₆₄ 3)
1)
t₆₆
1. The ST10F271 will complete the currently running bus cycle before granting bus access.
2. This is the first possibility for BREQ to become active.
3. The CS outputs will be resistive high (pull-up) after t₆₄.
165/173