SPEAR1340 Datasheet, PDF (157/200 Pages) STMicroelectronics – Dual-core Cortex A9 HMI embedded MPU

SPEAr1340
Timing characteristics
5.6
5.6.1
FSMC timing characteristics
This section describes the timing characteristics of the flexible static memory controller. The
FSMC can interface NAND Flash, NOR and SRAM. All the possible scenarios are described
below.
The timing characterization is performed assuming an output load capacitance of 10 pF on
all outputs.
NAND Flash configuration timing characteristics
Figure 21. NAND Flash configuration timing waveform
FSMC_CExn
FSMC_ALE_AD17
FSMC_CLE_AD16
FSMC_WEn
t_HCLK - t_ALE
t_HCLK - t_CLE
t_SET + t_W
t_WAIT
t_HOLD + t_W
FSMC_IO (ouT)
FSMC_REn
t_HIZ + t_D
t_SET + t_R
DATAOUT
t_HCLK - t_D
T_WAIT
t_HOLD + t_R
FSMC_IO (in)
t_MEM
DATAIN
t_MEM
T_ALE, T_CLE, T_W, T_R and T_D are fixed values: they depend only on the internal timings of
SPEAr.
T_SET, T_HOLD, T_WAIT and T_HIZ are programmable timings defined by FSMC registers. They
can be calculated as:
T_SET = (Set + 1) * T_HCLK (min value for Set is 0)
T_WAIT = (Wait + 1) * T_HCLK (min value for Wait is 1)
T_HOLD = (Hold + 1) * T_HCLK (min value for Hold is 1)
T_HIZ = Hiz * T_HCLK (min value for Hiz is 0)
T_HCLK = 6 ns (period of the AHB clock, the FSMC input clock)
T_MEM is the output delay of the NAND Flash.
When writing a data, since the NAND Flash strobes it on the rising edge of FSMC_WEn, the
user should choose the correct values of Set, Wait, Hold and Hiz in order to satisfy the
following constraints:
T_SET + T_W + T_WAIT - T_HIZ - T_D ≥ T_SETUP (NAND_FLASH)
T_HOLD + T_W - T_HCLK + T_D ≥ T_HOLD (NAND_FLASH)
Doc ID 023063 Rev 4
157/200