SPEAR1340 Datasheet, PDF (130/200 Pages) STMicroelectronics – Dual-core Cortex A9 HMI embedded MPU

Pin description
SPEAr1340
3.6
Strapping options
The following two tables show the strapping options available (STRAP[6:0]) on SPEAr1340.
STRAP[6:0] pins are sampled at reset release and they are reusable after the internal
latching for different purposes. When used as output pins, these pins require no special
conditions, but when used as input pins, the application must keep them in a non-driving (tri-
state) mode for at least 2 µs after MRESETn is released.
STRAP[6:0] pins are sampled by internal hardware logic during the power-on reset
sequence and latched on the BOOTSTRAP_CFG register in the MISC.
Table 37. Strapping options
Signal name
Description
Type Ball
STRAP0
S AE19
STRAP1
STRAP2
The BootROM firmware selects the booting device after reset release by
reading the status of the STRAP[3:0] pins.
S AH20
S AD19
STRAP3
STRAP4
STRAP5
STRAP6
Used to select the usage of NAND Flash 8-bit interface working as 3V3 or
1V8, along with CE0n:
STRAP4= 1 --> 3V3
STRAP4= 0 --> 1V8
Used to select the usage of NAND Flash extension to 16-bit interface
and/or second chip select CE1n working as 3V3 or 1V8:
STRAP5= 1 --> 3V3
STRAP5= 0 --> 1V8
Used to select the GMII/RGMII interface working at 3V3 or 2V5:
STRAP6= 1 --> 2V5
STRAP6= 0 --> 3V3
S AD20
S AE20
S AF20
S AG20
Table 38. Hardware boot selection (STRAP[0..3])
Primary source
Backup source⁽¹⁾
Bypass
Serial NOR Flash⁽²⁾
NAND Flash⁽³⁾
Parallel NOR Flash (8-bit)⁽³⁾
Parallel NOR Flash (16-bit)⁽³⁾
UART
rfu⁽⁴⁾
rfu
USB OTG (Device)
Serial NOR Flash⁽²⁾
NAND Flash⁽³⁾
na
USB OTG (Device)
USB OTG (Device)
USB OTG (Device)
USB OTG (Device)
na
na
na
na
UART
UART
STRAP3 STRAP2 STRAP1 STRAP0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
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Doc ID 023063 Rev 4