ST10F272M_12 Datasheet, PDF (151/176 Pages) STMicroelectronics – 16-bit MCU with 256 Kbyte Flash memory and 20 Kbyte RAM

ST10F272M
Electrical characteristics
Table 68. External clock drive
Parameter
Symbol
Direct drive
f_CPU = f_XTAL
Direct drive with
prescaler
f_CPU = f_XTAL/2
PLL usage
f_CPU = f_XTAL x F _Unit
Min
Max
Min
Max
Min
Max
XTAL1 period⁽¹⁾⁽²⁾ t_OSC SR
25
High time⁽³⁾
t₁ SR
6
Low time⁽³⁾
t₂ SR
6
Rise time⁽³⁾
t₃ SR
–
Fall time⁽³⁾
t₄ SR
–
–
83.3
250
83.3
250 ns
–
3
–
6
–
ns
–
3
–
6
–
ns
2
–
2
–
2
ns
2
–
2
–
2
ns
1. The minimum value for the XTAL1 signal period is considered the theoretical minimum. The real minimum
value depends on the duty cycle of the input clock signal.
2. 4 to 8 MHz is the input frequency range when using an external clock source. 40 MHz can be applied with
an external clock source only when direct drive mode is selected: in this case, the oscillator amplifier is
bypassed so it does not limit the input frequency.
3. The input clock signal must reach the defined levels V_IL2 and V_IH2.
Figure 49. External clock drive XTAL1
T_
T_
T_
6_)(
6_),
T_
T_/3#
'!0'2)
Note:
When direct drive is selected, an external clock source can be used to drive XTAL1. The
maximum frequency of the external clock source depends on the duty cycle: When 40 MHz
is used, 50% duty cycle is granted (low phase = high phase = 12.5 ns); when for instance
20 MHz is used, a 25 % duty cycle can be accepted (minimum phase, high or low, again
equal to 12.5 ns).
24.8.14
Memory cycle variables
The tables below use three variables which are derived from the BUSCONx registers and
represent the special characteristics of the programmed memory cycle. The following table
describes how these variables are to be computed.
Table 69. Memory cycle variables
Description
Symbol
ALE extension
t_A
Memory cycle time wait states
t_C
Memory tri-state time
t_F
Values
TCL x [ALECTL]
2TCL x (15 - [MCTC])
2TCL x (1 - [MTTC])
Doc ID 12968 Rev 3
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