ST10F272M_12 Datasheet, PDF (144/176 Pages) STMicroelectronics – 16-bit MCU with 256 Kbyte Flash memory and 20 Kbyte RAM

Electrical characteristics
ST10F272M
24.8.7
an external clock failure occurs, then the watchdog counter overflows (after 16 PLL clock
cycles).
The CPU clock signal will be switched to the PLL free-running clock signal, and the oscillator
watchdog interrupt request is flagged. The CPU clock will not switch back to the external
clock even if a valid external clock exits on XTAL1 pin. Only a hardware reset (or
bidirectional software/watchdog reset) can switch the CPU clock source back to direct clock
input.
When the OWD is disabled, the CPU clock is always the external oscillator clock (in direct
drive or prescaler operation) and the PLL is switched off to decrease consumption supply
current.
Phase locked loop (PLL)
For all other combinations of pins P0.15-13 (P0H.7-5) during reset the on-chip phase locked
loop is enabled and it provides the CPU clock (see Table 61). The PLL multiplies the input
frequency by the factor F which is selected via the combination of pins P0.15-13 (f_CPU =
f_XTAL x F). With every F’th transition of f_XTAL the PLL circuit synchronizes the CPU clock to
the input clock. This synchronization is done smoothly, so the CPU clock frequency does not
change abruptly.
Due to this adaptation to the input clock the frequency of f_CPU is constantly adjusted so it is
locked to f_XTAL. The slight variation causes a jitter of f_CPU which also effects the duration of
individual TCLs.
The timings listed in the AC characteristics that refer to TCLs therefore must be calculated
using the minimum TCL that is possible under the respective circumstances.
The real minimum value for TCL depends on the jitter of the PLL. The PLL tunes f_CPU to
keep it locked on f_XTAL. The relative deviation of TCL is the maximum when it is referred to
one TCL period.
This is especially important for bus cycles using wait states and for example, such as for the
operation of timers or serial interfaces. For all slower operations and longer periods (for
example, pulse train generation or measurement, or lower baudrates) the deviation caused
by the PLL jitter is negligible. Refer to next Section 24.8.9: PLL jitter for more details.
144/176
Doc ID 12968 Rev 3