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| ST10F272M_12 Datasheet, PDF (141/176 Pages) STMicroelectronics – 16-bit MCU with 256 Kbyte Flash memory and 20 Kbyte RAM | |||
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ST10F272M
Electrical characteristics
24.8
24.8.1
AC characteristics
Test waveforms
Figure 43. Input/output waveforms
6
6
6
4EST POINTS
24.8.2
6
6
6
!# INPUTS DURING TESTING ARE DRIVEN AT 6 FOR A LOGIC @ AND 6 FOR A LOGIC @
4IMING MEASUREMENTS ARE MADE AT 6)( MIN FOR A LOGIC @ AND 6), MAX FOR A LOGIC @
'!0'2)
Figure 44. Float waveforms
6/(
6,/!$ 6
6,/!$
6,/!$
6
4IMING
REFERENCE
POINTS
6/,
6/(
6
6/, 6
&OR TIMING PURPOSES A PORT PIN IS NO LONGER FLOATING WHEN 6,/!$ CHANGES OF Â M6
)T BEGINS TO FLOAT WHEN A M6 CHANGE FROM THE LOADED 6/(6/, LEVEL OCCURS )/()/, M!
'!0'2)
Definition of internal timing
The internal operation of the ST10F272M is controlled by the internal CPU clock fCPU. Both
edges of the CPU clock can trigger internal (for example, pipeline) or external (for example,
bus cycles) operations.
The specification of the external timing (AC characteristics) therefore depends on the time
between two consecutive edges of the CPU clock, called âTCLâ.
The CPU clock signal can be generated by different mechanisms. The duration of TCL and
its variation (and also the derived external timing) depends on the mechanism used to
generate fCPU.
This influence must be regarded when calculating the timings for the ST10F272M.
The example for PLL operation shown in Figure 45 refers to a PLL factor of 4.
The mechanism used to generate the CPU clock is selected during reset by the logic levels
on pins P0.15-13 (P0H.7-5).
Doc ID 12968 Rev 3
141/176
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