STM32F405XX_13 Datasheet, PDF (147/185 Pages) STMicroelectronics – ARM Cortex-M4 32b MCU+FPU, 210DMIPS, up to 1MB Flash/192+4KB RAM, USB OTG HS/FS

STM32F405xx, STM32F407xx
Electrical characteristics
Table 82. Synchronous non-multiplexed PSRAM write timings⁽¹⁾⁽²⁾
Symbol
Parameter
t_w(CLK)
t^d(CLKL-NExL)
FSMC_CLK period
FSMC_CLK low to FSMC_NEx low (x=0..2)
t_d(CLKL-NExH) FSMC_CLK low to FSMC_NEx high (x= 0…2)
t_{d(CLKL-NADVL)} FSMC_CLK low to FSMC_NADV low
t_{d(CLKL-NADVH)} FSMC_CLK low to FSMC_NADV high
t_d(CLKL-AV)
FSMC_CLK low to FSMC_Ax valid (x=16…25)
t_d(CLKL-AIV) FSMC_CLK low to FSMC_Ax invalid (x=16…25)
t_d(CLKL-NWEL) FSMC_CLK low to FSMC_NWE low
t_d(CLKL-NWEH) FSMC_CLK low to FSMC_NWE high
t_d(CLKL-Data) FSMC_D[15:0] valid data after FSMC_CLK low
t_d(CLKL-NBLH) FSMC_CLK low to FSMC_NBL high
t_{su(NWAIT-CLKH)} FSMC_NWAIT valid before FSMC_CLK high
t_{h(CLKH-NWAIT)} FSMC_NWAIT valid after FSMC_CLK high
1. C_L = 30 pF.
2. Based on characterization, not tested in production.
Min
2T_HCLK
-
1
-
6
-
6
-
2
-
3
4
0
Max Unit
-
ns
1
ns
-
ns
7
ns
-
ns
0
ns
-
ns
1
ns
-
ns
3
ns
-
ns
-
ns
-
ns
PC Card/CompactFlash controller waveforms and timings
Figure 63 through Figure 68 represent synchronous waveforms, and Table 83 and Table 84
provide the corresponding timings. The results shown in this table are obtained with the
following FSMC configuration:
• COM.FSMC_SetupTime = 0x04;
• COM.FSMC_WaitSetupTime = 0x07;
• COM.FSMC_HoldSetupTime = 0x04;
• COM.FSMC_HiZSetupTime = 0x00;
• ATT.FSMC_SetupTime = 0x04;
• ATT.FSMC_WaitSetupTime = 0x07;
• ATT.FSMC_HoldSetupTime = 0x04;
• ATT.FSMC_HiZSetupTime = 0x00;
• IO.FSMC_SetupTime = 0x04;
• IO.FSMC_WaitSetupTime = 0x07;
• IO.FSMC_HoldSetupTime = 0x04;
• IO.FSMC_HiZSetupTime = 0x00;
• TCLRSetupTime = 0;
• TARSetupTime = 0.
In all timing tables, the T_HCLK is the HCLK clock period.
DocID022152 Rev 4
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