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| STM32F405XX_13 Datasheet, PDF (114/185 Pages) STMicroelectronics – ARM Cortex-M4 32b MCU+FPU, 210DMIPS, up to 1MB Flash/192+4KB RAM, USB OTG HS/FS | |||
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Electrical characteristics
STM32F405xx, STM32F407xx
Table 50. NRST pin characteristics
Symbol
Parameter
Conditions Min Typ Max Unit
VIL(NRST)(1) NRST Input low level voltage
VIH(NRST)(1) NRST Input high level voltage
VIL(NRST)(1) NRST Input low level voltage
VIH(NRST)(1) NRST Input high level voltage
TTL ports
-
-
0.8
2.7 V ⤠VDD
⤠3.6 V
2
-
-
V
CMOS ports
-
0.3VDD
1.8 V ⤠VDD
⤠3.6 V
0.7VDD
-
Vhys(NRST)
NRST Schmitt trigger voltage
hysteresis
-
200
-
mV
RPU
Weak pull-up equivalent resistor(2) VIN = VSS
30
40
50
kΩ
VF(NRST)(1) NRST Input filtered pulse
-
-
100
ns
VNF(NRST)(1) NRST Input not filtered pulse
VDD > 2.7 V 300
-
-
ns
TNRST_OUT Generated reset pulse duration
Internal
Reset source
20
-
-
µs
1. Guaranteed by design, not tested in production.
2.
The pull-up is designed
the series resistance must
with a true
be minimum
r(e~s1i0st%anocredeinr)s.eries
with
a
switchable
PMOS.
This
PMOS
contribution
to
Figure 38. Recommended NRST pin protection
External
reset circuit(1)
VDD
NRST(2)
RPU
0.1 μF
Internal Reset
Filter
5.3.18
STM32Fxxx
ai14132c
1. The reset network protects the device against parasitic resets.
2.
The user must ensure that the level
Table 50. Otherwise the reset is not
on the NRST pin can go below the
taken into account by the device.
VIL(NRST)
max
level
specified
in
TIM timer characteristics
The parameters given in Table 51 and Table 52 are guaranteed by design.
Refer to Section 5.3.16: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).
114/185
DocID022152 Rev 4
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