START499D Datasheet, PDF (14/18 Pages) STMicroelectronics – NPN RF silicon transistor

Package mechanical data
START499D
6.1
Thermal pad and via design
Thernal vias are required in the PCB layout to effectively conduct heat away from the
package. The via pattern has been designed to address thermal, power dissipation and
electrical requirements of the device.
The via pattern is based on thru-hole vias with 0.203 mm to 0.330 mm finished hole size on
a 0.5 mm to 1.2 mm grid pattern with 0.025 plating on via walls. If micro vias are used in a
design, it is suggested that the quantity of vias be increased by a 4:1 ratio to achieve similar
results.
Figure 20. Pad layout details
SOT-89
14/18
Doc ID 14496 Rev 4