STAP16DPPS05 Datasheet, PDF (13/33 Pages) STMicroelectronics – Low voltage 16-bit constant current LED sink driver

STAP16DPPS05
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Timing diagrams
Timing diagrams
Note:
Table 9. Truth table
CLOCK LE/DM1 OE/DM2 SERIAL-IN OUT0............. OUT7................ OUT15
H
L
Dn
Dn ..... Dn - 7 ..... Dn -15
L
L
Dn + 1
No change
H
L
Dn + 2
X
L
Dn + 3
Dn + 2 ..... Dn - 5 ..... Dn -13
Dn + 2 ..... Dn - 5 ..... Dn -13
X
H
Dn + 3
OFF
SDO
Dn - 15
Dn - 14
Dn - 13
Dn - 13
Dn - 13
OUTn = ON when Dn = H OUTn = OFF when Dn = L.
Figure 7. Timing diagram
Note:
Latch and output enable terminals are level-sensitive and are not synchronized with rising or
falling edge of LE/DM1 signal. When LE/DM1 terminal is low level, the latch circuit holds
previous set of data. When LE/DM1 terminal is high level, the latch circuit refreshes new set
of data from SDI chain. When OE/DM2 terminal is at low level, the output terminals Out 0 to
Out 15 respond to data in the latch circuits, either ‘1’ ON or ‘0’ OFF. When OE/DM2 terminal
is at high level, all output terminals are switched OFF.
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