STAP16DPPS05 Datasheet, PDF (10/33 Pages) STMicroelectronics – Low voltage 16-bit constant current LED sink driver

Electrical characteristics
STAP16DPPS05
V_DD = 5 V, T_j = 25 °C, unless otherwise specified.
Symbol
Parameter
Table 8. Switching characteristics⁽¹⁾⁽²⁾
Test conditions
Min. Typ. Max. Unit
f_clk
t_PLH1
Clock frequency
CLK-OUTn, LE/DM1 = H,
OE/DM2 = L
Cascade operation
LE/DM1-OUTn,
t_{PLH2 OE/DM2 = L}
t_PLH3
OE/DM2-OUTn, LE\DM1 =
H
t_PLH CLK-SDO
t_PHL1
CLK-OUTn,
LE/DM1 = H,
OE/DM2 = L
LE/DM1-OUTn,
t_{PHL2 OE/DM2 = L}
OE/DM2-OUTn,
t_{PHL3 LE/DM1 = H}
V_IH = V_DD
V_IL = GND C_L = 10 pF
I_O = 20 mA V_L = 3.0 V
R_L = 60 Ω
t_PHL CLK-SDO
Output rise time
t_ON 10~90% of voltage
waveform
V_DD = 3.3 V
V_DD = 5 V
V_DD = 3.3 V
V_DD = 5 V
V_DD = 3.3 V
V_DD = 5 V
V_DD = 3.3 V
V_DD = 5 V
V_DD = 3.3 V
V_DD = 5 V
V_DD = 3.3 V
V_DD = 5 V
V_DD = 3.3 V
V_DD = 5 V
V_DD = 3.3 V
V_DD = 5 V
V_DD = 3.3 V
V_DD = 5 V
30 MHz
55 90
ns
30 50
48 80
ns
30 45
70 120
ns
45 65
21 35
ns
15 25
28 35
ns
22 40
13 35
ns
12 18
24 35
ns
21 30
24 40
ns
17 25
30 55
ns
10 20
Output fall time
t_OFF 90~10% of voltage
waveform
V_DD = 3.3 V
V_DD = 5 V
4
10
ns
3
8
t_r
CLK rise time ⁽³⁾
t_f
CLK fall time ⁽³⁾
5
µs
5
1. All table limits are guaranteed by design.
2. Not tested in production.
3. If devices are connected in cascade and tr or tf is large, it may be critical to achieve the timing required for data transfer
between two cascaded devices.
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