M69KB096AB Datasheet, PDF (13/73 Pages) STMicroelectronics – 64 Mbit (4Mb x 16), 104MHz Clock Rate, 1.8V Supply, Bare Die, Burst PSRAM

M69KB096AB
3 Power-up
3 Power-up
To guarantee correct operation, a specific Power-Up sequence must be followed to initialize the
M69KB096AB. Power must be applied simultaneously to V_CC and V_CCQ. Once V_CC and V_CCQ
have reached a stable level (see Figure 35: Deep Power-Down Entry and Exit AC Waveforms
and Figure 34: Power-Up AC Waveforms), the device will require t_VCHEL to complete its self-
initialization process. During the initialization period, the E signal must remain High. Once
initialization has completed, the device is ready for normal operation.
Initialization will load the Bus Configuration Register (BCR) and the Refresh Configuration
Register (RCR) with their default settings (see Table 9: Bus Configuration Register Definition,
and Table 11: Refresh Configuration Register Definition).
4 Low-power modes
4.1 Standby
When the device is in Standby, the current consumption is reduced to the level necessary to
perform the memory array refresh operation. The device will enter Standby when a read or
write operation is completed, depending on the operating mode (Asynchronous, NOR-Flash
Synchronous or Full Synchronous).
For details on how to enter Standby, refer to Table 3: Standard Asynchronous Operating
Modes, Table 5: Asynchronous Write Operations (NOR-Flash Synchronous Mode) and Table 6:
Synchronous Read Operations (NOR-Flash Synchronous Mode).
4.2 Deep Power-Down
Deep Power-Down (DPD) is used by the system memory microcontroller to disable the PSRAM
device when its storage capabilities are not needed. All refresh operations are then disabled.
For the device to enter Deep Power-Down, bit 4 of the RCR must be set to ‘0’ and Chip Enable,
E, must go High, V_IH. When the Deep Power-Down is enabled, the data stored in the device
may be corrupted and BCR, RCR and DIDR content are saved.
For the device exits Deep Power-Down by driving Chip Enable, E, Low, V_IL. Bit 4 of the RCR will
be automatically set to ‘1’. Once the Deep Power-Down is exited, the device will be available for
normal operations after t_VCHEL (time to perform an initialization sequence) During this delay, the
current consumption will be higher than the specified Standby levels, but considerably lower
than the active current. The content of the registers will be restored after Deep Power-Down.
For details on how to enter Deep Power-Down, refer to Table 3: Standard Asynchronous
Operating Modes, Table 5: Asynchronous Write Operations (NOR-Flash Synchronous Mode)
and Table 6: Synchronous Read Operations (NOR-Flash Synchronous Mode).
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