BLUENRG-1 Datasheet, PDF (128/173 Pages) STMicroelectronics – Bluetooth low energy wireless system-on-chip

Functional details
BlueNRG-1
Table 158: MFTX - TNICTRL register description: address offset MFTX_BASE_ADDR+0x1C
Bit Field name Reset RW Description
0
TNAPND
0x0
R
Timer interrupt A pending:· 0: No interrupt source pending. · 1:
Interrupt source pending.
1
TNBPND
0x0
R
Timer interrupt B pending:· 0: No interrupt source pending. · 1:
Interrupt source pending.
2
TNCPND
0x0
R
Timer interrupt C pending:· 0: No interrupt source pending. · 1:
Interrupt source pending.
3
TNDPND
0x0
R
Timer interrupt D pending:· 0: No interrupt source pending. · 1:
Interrupt source pending.
4
TNAIEN
0x0
RW
Timer interrupt A enable:· 0: Interrupt disabled. · 1: Interrupt
enabled.
5
TNBIEN
0x0
RW
Timer interrupt B enable:· 0: Interrupt disabled. · 1: Interrupt
enabled.
6
TNCIEN
0x0
RW
Timer interrupt C enable:· 0: Interrupt disabled. · 1: Interrupt
enabled
7
TNDIEN
0x0
RW
Timer interrupt D enable:· 0: Interrupt disabled. · 1: Interrupt
enabled.
31:8 RESERVED 0x0 R RESERVED
Table 159: MFTX - TNICLR register description: address offset MFTX_BASE_ADDR+0x20
Bit
Field name
Reset
RW Description
0
TNACLR
0x0
W
1: clear the timer pending flag A
1
TNBCLR
0x0
W
1: clear the timer pending flag B.
2
TNCCLR
0x0
W
1: clear the timer pending flag C.
3
TNDCLR
0x0
W
1: clear the timer pending flag D.
31:4 RESERVED
0x0
R
RESERVED
3.14
3.14.1
Watchdog
Introduction
The watchdog timer provides a way of recovering from software crashes.
The watchdog monitors the interrupt and asserts a Reset signal if the interrupt remains
unserved for the entire programmed period.
The watchdog clock is used to generate a regular interrupt, depending on a programmed
value. It is counting down at a fixed frequency around 32.768 kHz provided either by
embedded RCO or by the external XO 32 kHz.
Main features are:
 32-bit down counter at fixed frequency 32.768 kHz
 Generate an interrupt each time the counter reaches zero
 Generate an internal reset that reboot the system if the generated interrupt is not
cleared by software and a second interrupt occurs
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