TDA7439_08 Datasheet, PDF (12/23 Pages) STMicroelectronics – Three-band digitally-controlled audio processor

I²C bus interface
Figure 12. Timing diagram of the data on the I²C bus
SCL
SDA
Data stable Data can change
when clock high when clock low
Figure 13. Timing diagram of the start/stop
TDA7439
SCL
SDA
Start
Stop
Figure 14. Timing diagram of the acknowledge
SCL
1
2
6
7
8
9
SDA
Start
MSB
Acknowledge
from receiver
4.6
Interface protocol
The interface protocol comprises:
" a start condition (S)
" a chip-address byte, containing the TDA7439 address
" a sub-address byte including an auto address-increment bit
" a sequence of data bytes (N bytes + acknowledge)
" a stop condition (P).
Figure 15. SDA addressing and data
CHIP ADDRESS
SUBADDRESS
DATA 1 to DATA n
MSB
LSB
MSB
S 1 0 0 0 1 0 0 0 ACK X X X B
D96AU420
LSB
MSB
DATA
ACK
DATA
LSB
ACK P
S = Start, ACK = Acknowledge, B = Auto increment, P = Stop
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