TDA7439_08 Datasheet, PDF (11/23 Pages) STMicroelectronics – Three-band digitally-controlled audio processor

TDA7439
4
I²C bus interface
I²C bus interface
Data transmission from the microprocessor to the TDA7439 and vice versa takes place
through the 2-wire I²C bus interface. This consists of the data and clock lines, SDA and SCL.
Pull-up resistors to the positive supply voltage must be used (there are no internal pull-ups).
4.1
Data validity
The data on the SDA line must be stable during the high period of the clock as shown in
Figure 12. SDA is allowed to change only when SCL is low.
4.2
Start and stop conditions
As shown in Figure 13 a start condition is a high to low transition of SDA while SCL is high.
The stop condition is a low to high transition of SDA while SCL is high.
4.3
Byte format
Every byte transferred on the SDA line must contain 8 bits. The MSB is transferred first.
There is also provision for an acknowledge bit to follow each byte to indicate that the data
has been received.
4.4
Acknowledge
The master (µP) puts a resistive high level on SDA during the acknowledge clock pulse (see
Figure 14). The peripheral (audio processor) that acknowledges has to pull down (low) the
SDA line during this clock pulse.
The audio processor which has been addressed has to generate an acknowledge after the
reception of each byte, otherwise the SDA line remains at the high level during the ninth
clock pulse time. In this case the master transmitter can generate the STOP information in
order to abort the transfer.
4.5
Transmission without acknowledge
Suppressing the audio processor acknowledge detection enables the µP to use a simpler
transmission: it simply waits for one clock, without checking the slave acknowledging, and
then sends the new data.
This approach has, of course, less protection from transmission errors.
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