STCH02 Datasheet, PDF (12/24 Pages) STMicroelectronics – Offline PWM controller for ultra-low standby adapters

Application information
STCH02
3.1
Gate driver
The gate driver of the power MOSFET is designed to supply a controlled gate current during
both turn-on and turn-off in order to minimize the common mode EMI. Under UVLO
conditions an internal pull-down circuit holds the gate low in order to ensure that the power
MOSFET cannot be turned on accidentally.
3.2
Frequency jittering for EMI reduction
Although the STCH02 device works in the QR mode and the switching frequency is already
modulated at twice of the mains frequency, dedicated frequency jittering circuitry is
embedded inside the IC to further reduce the EMI filtering. A proprietary frequency jitter
technique is implemented in the controller, based on the injection of a modulating signal at
9 kHz (above the feedback loop bandwidth) with 50% duty cycle on the current sense
signal: this signal is a square waveform that modulates the amplitude of the peak primary
current. The percentage of this amplitude is set as a default at 5%. As the peak current
reduces with decreasing load levels, the effect of this modulation automatically attenuates at
lower loads, where the energy of EMI noise is highly reduced.
3.3
High voltage start-up generator
Based on a 650 V rated depletion MOSFET embedded into the startup cell, the HV current
generator is supplied through the DRAIN pin and is enabled only if the voltage on the HV pin
is higher than the HVSTART threshold (50 V typical value).
With reference to the timing diagram in Figure 6, when the power is applied to the circuit and
the voltage on the input bulk capacitor is high enough, the HV generator is sufficiently
biased to start operating, thus it will draw the current I_CHARGE (7 mA typ. value) through the
HV pin and will charge the capacitor connected between the V_DD pin and ground. This
charging current will be reduced at 0.6 mA in case the voltage on the V_DD is lower than
V_DD-FOLD, in order to prevent exceeding IC dissipation when the pin is accidentally shorted
to ground or during a restart after protection triggering.
As the V_DD voltage reaches the start-up threshold (13 V typ.) the chip starts operating and
the control logic disables the HV generator.
While the generator is off, there are virtually no losses across the HV startup cell, except
a few hundreds nA of the leakage current through the depletion MOSFET.
The IC is powered by the energy stored in the V_DD capacitor until the self-supply circuit
(typically an auxiliary winding of the transformer and a steering diode) develops a voltage
high enough to sustain the operation.
The chip is able to power itself directly from the rectified mains: when the voltage on the V_DD
pin falls below V_DD-OFF (10 V typ.), the HV current generator is turned on and charges the
supply capacitor until it reaches the V_DD-ON threshold.
In this way, the self-supply circuit develops a voltage high enough to sustain the operation of
the device. This feature is useful especially during the CC regulation, when the flyback
voltage generated by the auxiliary winding alone may not be able to keep V_DD within the
operative range.
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