M69KB128AA Datasheet, PDF (11/68 Pages) STMicroelectronics – 128 Mbit (8Mb x16) 1.8V Supply, Burst PSRAM

M69KB128AA
2 Signal descriptions
2.8 Lower Byte Enable (LB)
The Lower Byte Enable, LB, gates the data on the Lower Byte Data Inputs/Outputs (DQ0-DQ7)
to or from the lower part of the selected address during a write or read operation.
If both LB and UB are disabled (High), the device will disable the data bus from receiving or
transmitting data. Although the device will seem to be deselected, it remains in an active mode
as long as E remains Low.
2.9 Clock Input (K)
The Clock, K, is an input signal to synchronize the memory to the microcontroller or system bus
frequency during Synchronous Burst Read and Write operations. The Clock input signal
increments the device internal address counter.
The addresses are latched on the rising edge of the Clock K, when L is Low during
Synchronous Bus operations.
Latency counts are defined from the first Clock rising edge after L falling edge to the first data
input latched or the first data output valid.
The Clock input is required during all synchronous operations and must be kept Low during
asynchronous operations.
2.10 Configuration Register Enable (CR)
When this signal is driven High, V_IH, bus read or write operations access either the value of the
Refresh Configuration Register (RCR) or the Bus Configuration Register (BCR) according to
the value of A19.
2.11 Latch Enable (L)
In Synchronous mode, addresses are latched on the rising edge of the Clock K when the Latch
Enable input, L is Low. In Asynchronous mode, addresses are latched on L rising edge.
2.12 Wait (WAIT)
The WAIT output signal provides data-valid feedback during Synchronous Burst Read and
Write operations. The signal is gated by E. Driving E High while WAIT is asserted may cause
data corruption.
Once a read or write operation has been initiated, the WAIT signal goes active to indicate that
the M69KB128AA device requires additional time before data can be transferred.
The WAIT signal also is used for arbitration when a Read or Write operation is launched while
an on-chip refresh is in progress (see Figure 6: Refresh Collision during Synchronous Read
Operation in Variable Latency mode).
Typically, the WAIT pin of the M69KB128AA can be connected to a shared WAIT signal used by
the processor to coordinate transactions with multiple memories on the synchronous bus.
See Section 3: Power-up for details on the WAIT signal operation.
11/68