ST10F276E Datasheet, PDF (106/235 Pages) STMicroelectronics – 16-bit MCU with MAC unit 832 Kbyte Flash memory and 68 Kbyte RAM

System reset
19 System reset
ST10F276E
System reset initializes the MCU in a predefined state. There are six ways to activate a reset
state. The system start-up configuration is different for each case as shown in Table 60.
Table 60. Reset event definition
Reset source
Flag RPD status
Conditions
Power-on reset
Asynchronous Hardware reset
Synchronous Long Hardware reset
PONR
LHWR
Synchronous Short Hardware reset SHWR
Watchdog Timer reset
Software reset
WDTR
SWR
Low
Low
High
High
(3)
(3)
Power-on
t_RSTIN >⁽¹⁾
t_RSTIN > (1032 + 12) TCL + max(4 TCL, 500ns)⁽²⁾
t_RSTIN > max(4 TCL, 500ns)
t_RSTIN < (1032 + 12) TCL + max(4 TCL, 500ns)⁽²⁾
WDT overflow
SRST instruction execution
1. RSTIN pulse should be longer than 500ns (Filter) and than settling time for configuration of Port0.
2. See next Section 19.1 for more details on minimum reset pulse duration.
3. The RPD status has no influence unless Bidirectional Reset is activated (bit BDRSTEN in SYSCON): RPD low inhibits the
Bidirectional reset on SW and WDT reset events, that is RSTIN is not activated (refer to sections 19.4, 19.5 and 19.6).
19.1
Input filter
On RSTIN input pin an on-chip RC filter is implemented. It is sized to filter all the spikes
shorter than 50ns. On the other side, a valid pulse shall be longer than 500ns to grant that
ST10 recognizes a reset command. In between 50ns and 500ns a pulse can either be
filtered or recognized as valid, depending on the operating conditions and process
variations.
For this reason all minimum durations mentioned in this Chapter for the different kind of
reset events shall be carefully evaluated taking into account of the above requirements.
In particular, for Short Hardware Reset, where only 4 TCL is specified as minimum input
reset pulse duration, the operating frequency is a key factor. Examples:
● For a CPU clock of 64 MHz, 4 TCL is 31.25ns, so it would be filtered. In this case the
minimum becomes the one imposed by the filter (that is 500ns).
● For a CPU clock of 4 MHz, 4 TCL is 500ns. In this case the minimum from the formula
is coherent with the limit imposed by the filter.
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