ST10F273 Datasheet, PDF (102/179 Pages) STMicroelectronics – 16-bit MCU with 512 Kbyte Flash memory and 36 Kbyte RAM

System reset
ST10F273
20.9 Reset summary
A summary of the different reset events is reported in the table below.
Table 50. Reset event
RSTIN
Event
min
max
WDTCON Flags
Power-on reset
Hardware reset
(asynchronous)
Short hardware
reset
(synchronous) ⁽¹⁾
Long hardware
reset
(synchronous)
1 ms (VREG)
1.2 ms
0 0 N Asynch.
(Reson. + PLL)
-
10.2 ms
(Crystal + PLL)
0 1 N Asynch.
1ms (VREG)
-
1xx
FORBIDDEN
x xY
NOT APPLICABLE
0 0 N Asynch.
500ns
-
0 1 N Asynch.
500ns
-
0 0 Y Asynch.
500ns
-
0 1 Y Asynch.
500ns
-
1 0 N Synch.
max (4 TCL, 500ns)
1032 + 12 TCL +
max(4 TCL, 500ns)
1 1 N Synch.
max (4 TCL, 500ns)
1032 + 12 TCL +
max(4 TCL, 500ns)
1 0 Y Synch.
max (4 TCL, 500ns)
1032 + 12 TCL +
max(4 TCL, 500ns)
Activated by internal logic for 1024 TCL
1 1 Y Synch.
max (4 TCL, 500ns)
1032 + 12 TCL +
max(4 TCL, 500ns)
Activated by internal logic for 1024 TCL
1 0 N Synch.
1032 + 12 TCL +
max(4 TCL, 500ns)
-
1 1 N Synch.
1032 + 12 TCL +
max(4 TCL, 500ns)
-
1 0 Y Synch.
1032 + 12 TCL +
max(4 TCL, 500ns)
-
Activated by internal logic only for 1024 TCL
1 1 Y Synch.
1032 + 12 TCL +
max(4 TCL, 500ns)
-
Activated by internal logic only for 1024 TCL
11110
11110
01110
01110
01110
01110
00110
00110
00110
00110
01110
01110
01110
01110
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