SST89E564RD_03 Datasheet, PDF (77/86 Pages) Silicon Storage Technology, Inc – FlashFlex51 MCU

FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
TABLE 13-11: EXTERNAL MODE FLASH MEMORY PROGRAMMING/VERIFICATION PARAMETERS¹
Parameter^2,3
Symbol
Min
Max
Reset Setup Time
T_SU
3
Read-ID Command Width
T_RD
1
PSEN# Setup Time
T_ES
40
Address, Command, Data Setup Time
T_ADS
0
Chip-Erase Time
T_CE
150
Block-Erase Time
T_BE
100
Sector-Erase Time
T_SE
30
Program Setup Time
T_PROG
1.2
Address, Command, Data Hold
T_DH
0
Byte-Program Time⁴
T_PB
50
Select-Block Program Time
T_PSB
500
Re-map or Security bit Program Time
T_PS
80
Verify Command Delay Time
T_OA
50
Verify High Order Address Delay Time
T_AHA
50
Verify Low Order Address Delay Time
T_ALA
50
1. For IAP operations, the program execution overhead must be added to the above timing parameters.
2. Program and Erase times will scale inversely proportional to programming clock frequency.
3. All timing measurements are from the 50% of the input to 50% of the output.
4. Each byte must be erased before programming.
Data Sheet
Units
µs
µs
µs
ns
ms
ms
ms
µs
ns
µs
ns
µs
ns
ns
ns
T13-11.1 1207
©2003 Silicon Storage Technology, Inc.
77
S71207-04-000
12/03