SST89E564RD_03 Datasheet, PDF (1/86 Pages) Silicon Storage Technology, Inc – FlashFlex51 MCU

FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
FEATURES:
SST89E/V564RD SST89E/VE554RC FlashFlex51 MCU
Data Sheet
• 8-bit 8051-Compatible Microcontroller (MCU)
with Embedded SuperFlash Memory
– Fully Software Compatible
– Development Toolset Compatible
– Pin-For-Pin Package Compatible
• SST89E564RD/SST89E554RC Operation
– 0 to 40 MHz at 5V
• SST89V564RD/SST89V554RC Operation
– 0 to 33 MHz at 3V
• Total 1 KByte Internal RAM (256 Byte + 768 Byte)
• Dual Block SuperFlash EEPROM
– SST89E564RD/SST89V564RD:
64 KByte primary block + 8 KByte secondary
block (128-Byte sector size for both blocks)
– SST89E554RC/SST89V554RC:
32 KByte primary block + 8 KByte secondary
block (128-Byte sector size for both blocks)
– Individual Block Security Lock with SoftLock
– Concurrent Operation during
In-Application Programming (IAP)
– Memory Overlay for Interrupt Support
during IAP
• Support External Address Range up to 64
KByte of Program and Data Memory
• Three High-Current Port 1 pins (16 mA each)
• Three 16-bit Timers/Counters
• Full-Duplex, Enhanced UART
– Framing error detection
– Automatic address recognition
• Eight Interrupt Sources at 4 Priority Levels
• Programmable Watchdog Timer (WDT)
• Programmable Counter Array (PCA)
• Four 8-bit I/O Ports (32 I/O Pins)
• Second DPTR register
• Low EMI Mode (Inhibit ALE)
• SPI Serial Interface
• Standard 12 Clocks per cycle, the device has an
option to double the speed to 6 clocks per cycle.
• TTL- and CMOS-Compatible Logic Levels
• Brown-out Detection
• Low Power Modes
– Power-down Mode with External Interrupt Wake-up
– Idle Mode
• PDIP-40, PLCC-44 and TQFP-44 Packages
• Temperature Ranges:
– Commercial (0°C to +70°C)
– Industrial (-40°C to +85°C)
PRODUCT DESCRIPTION
The SST89E564RD, SST89V564RD, SST89E554RC, and
SST89V554RC are members of the FlashFlex51 family of 8-
bit microcontroller products designed and manufactured with
the state-of-the-art SuperFlash CMOS semiconductor pro-
cess technology. The devices use the 8051 instruction set
and are pin-for-pin compatible with standard 8051 microcon-
troller devices.
The device comes with 72/40 KByte of on-chip flash
EEPROM program memory using SST’s patented and pro-
prietary CMOS SuperFlash EEPROM technology with the
SST’s field-enhancing, tunneling injector, split-gate mem-
ory cells. The SuperFlash memory is partitioned into 2
independent program memory blocks. The primary Super-
Flash Block 0 occupies 64/32 KByte of internal program
memory space and the secondary SuperFlash Block 1
occupies 8 KByte of internal program memory space. The
8-KByte secondary SuperFlash block can be mapped to
the lowest location of the 64/32 KByte address space; it
can also be hidden from the program counter and used as
an independent EEPROM-like data memory. The flash
memory blocks can be programmed via a standard 87C5x
OTP EPROM programmer fitted with a special adapter and
firmware for SST’s device. During the power-on reset, the
device can be configured as a slave to an external host for
source code storage or as a master to an external host for
an in-application programming (IAP) operation. The device
is designed to be programmed in-system and in-application
on the printed circuit board for maximum flexibility. The
device is pre-programmed with an example of the boot-
strap loader in the memory, demonstrating the initial user
program code loading or subsequent user code updating
via the IAP operation. An example bootstrap loader is avail-
able for the user’s reference and convenience only. SST
does not guarantee the functionality or the usefulness of
the sample bootstrap loader. Chip-Erase operations will
erase the pre-programmed sample code.
In addition to 72/40 KByte of SuperFlash EEPROM pro-
gram memory on-chip, the device can address up to 64
KByte of external program memory. In addition to 1024 x8
bits of on-chip RAM, up to 64 KByte of external RAM can
be addressed.
SST’s highly reliable, patented SuperFlash technology and
memory cell architecture have a number of important
advantages for designing and manufacturing flash
EEPROMs. These advantages translate into significant
cost and reliability benefits for our customers.
©2003 Silicon Storage Technology, Inc.
S71207-04-000
12/03
1
The SST logo, SuperFlash, and FlashFlex are registered trademarks of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.