SST89E564RD_03 Datasheet, PDF (68/86 Pages) Silicon Storage Technology, Inc – FlashFlex51 MCU

FlashFlex51 MCU
SST89E564RD / SST89V564RD / SST89E554RC / SST89V554RC
Data Sheet
1. Under steady state (non-transient) conditions, I_OL must be externally limited as follows:
Maximum I_OL per port pin:
15mA
Maximum I_OL per 8-bit port:26mA
Maximum I_OL total for all outputs:71mA
If I_OL exceeds the test condition, V_OL may exceed the related specification.
Pins are not guaranteed to sink current greater than the listed test conditions.
2. Capacitive loading on Ports 0 & 2 may cause spurious noise to be superimposed on the V_OLs of ALE and Ports 1 & 3. The noise due
to external bus capacitance discharging into the Port 0 & 2 pins when the pins make 1-to-0 transitions during bus operations. In the
worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to
qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input.
3. Load capacitance for Port 0, ALE & PSEN#= 100pF, load capacitance for all other outputs = 80pF.
4. Capacitive loading on Ports 0 & 2 may cause the V_OH on ALE and PSEN# to momentarily fall below the V_DD - 0.7 specification when
the address bits are stabilizing.
5. Pins of Ports 1, 2 & 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its
maximum value when V_IN is approximately 2V.
6. Pin capacitance is characterized but not tested. EA# is 25pF (max).
TABLE 13-7: DC ELECTRICAL CHARACTERISTICS FOR SST89V564RD AND SST89V554RC
T_a = -40°C TO +85°C; V_DD = 2.7-3.6V; V_SS = 0V (1 OF 2)
Symbol Parameter
Test Conditions
Min
V_IL
V_IH
V_IH1
V_OL
V_OL
V_OL1
V_OH
V_OH1
V_BOD
I_IL
I_TL
I_LI
R_RST
C_IO
Input Low Voltage
Input High Voltage
Input High Voltage (XTAL1, RST)
Output Low Voltage (Ports 1.5, 1.6, 1.7)
Output Low Voltage (Ports 1, 2, 3)¹
Output Low Voltage (Port 0, ALE, PSEN#)^1,3
Output High Voltage (Ports 1, 2, 3, ALE, PSEN#)⁴
Output High Voltage (Port 0 in External Bus Mode)⁴
Brown-out Detection Voltage
Logical 0 Input Current (Ports 1, 2, 3)
Logical 1-to-0 Transition Current (Ports 1, 2, 3)⁵
Input Leakage Current (Port 0)
RST Pull-down Resistor
Pin Capacitance⁶
2.7 < V_DD < 3.6
2.7 < V_DD < 3.6
2.7 < V_DD < 3.6
V_DD = 2.7V
I_OL = 16mA
V_DD = 2.7V
I_OL = 100µA²
I_OL = 1.6mA²
I_OL = 3.5mA²
V_DD = 2.7V
I_OL = 200µA²
I_OL = 3.2mA²
V_DD = 2.7V
I_OH = -10µA
I_OH = -30µA
I_OH = -60µA
V_DD = 2.7V
I_OH = -200µA
I_OH = -3.2mA
V_IN = 0.4V
V_IN = 2V
0.45 < V_IN < V_DD-0.3
-0.5
0.2V_DD + 0.9
0.7V_DD
V_DD - 0.3
V_DD - 0.7
V_DD - 1.5
V_DD - 0.3
V_DD - 0.7
2.35
@ 1 MHz, 25°C
Max
0.7
V_DD + 0.5
V_DD + 0.5
1.0
0.3
0.45
1.0
0.3
0.45
2.55
-75
-650
±10
225
15
Units
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
µA
µA
µA
KΩ
pF
©2003 Silicon Storage Technology, Inc.
68
S71207-04-000
12/03