SST89E58RD2 Datasheet, PDF (36/91 Pages) Silicon Storage Technology, Inc – FlashFlex51 MCU

FlashFlex51 MCU
SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2
SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2
Preliminary Specifications
TABLE 4-2: EXTERNAL HOST MODE COMMANDS FOR SST89E/V516RD2
Operation
PROG#/
P3[5:4]
RST PSEN# ALE EA# P3[7] P3[6] P2[7] P2[6] P0[7:0] P2[5:0] P1[7:0]
Read-ID
Chip-Erase
V_IH1
V_IL
V_IH1
V_IL
V_IH
V_IH
V_IL
V_IL
V_IL
V_IL
DO
AH
AL
⇓¹
V_IH
V_IL
V_IL
V_IL
V_IH
X
X
X
Block-Erase
Sector-Erase
Byte-Program
V_IH1
V_IL
V_IH1
V_IL
V_IH1
V_IL
⇓
V_IH V_IH
V_IH
V_IL
V_IH
X
X
X
⇓
V_IH
V_IH
V_IL
V_IH
V_IH
X
AH
AL
⇓
V_IH V_IH
V_IH
V_IH
V_IL
DI
AH
AL
Byte-Verify (Read)
Select-Block0
Select-Block1
V_IH1
V_IL
V_IH1
V_IL
V_IH1
V_IL
V_IH
V_IH V_IH
V_IH
V_IL
V_IL
DO
AH
AL
⇓
V_IH
V_IH
V_IL
V_IL
V_IH
X
55H
X
⇓
V_IH V_IH
V_IL
V_IL
V_IH
X
A5H
X
Prog-SC0
Prog-SB1
Prog-SB2
V_IH1
V_IL
V_IH1
V_IL
V_IH1
V_IL
⇓
V_IH V_IH
V_IL
V_IL
V_IH
X
5AH
X
⇓
V_IH
V_IH
V_IH
V_IH
V_IH
X
X
X
⇓
V_IH
V_IL
V_IL
V_IH
V_IH
X
X
X
Prog-SB3
V_IH1
V_IL
⇓
V_IH
V_IL
V_IH
V_IL
V_IH
X
X
X
Enable-Clock-Double V_IH1 V_IL
⇓
V_IH V_IH
V_IL
V_IL
V_IL
X
55H
X
T4-2.0 1255
1. Symbol ⇓ signifies a negative pulse and the command is asserted during the low state of PROG#/ALE input. All other combinations
of the above input pins are invalid and may result in unexpected behaviors.
Note: V_IL = Input Low Voltage; V_IH = Input High Voltage; V_IH1 = Input High Voltage (XTAL, RST); X = Don’t care; AL = Address low order byte;
AH = Address high order byte; DI = Data Input; DO = Data Output
VSS VDD RST
Ready/Busy#
Address Bus ^A14
A15-A14 _A15
Flash
Control Signals
0
Port 0 ₆
7
0
0
1
1
2
2
Port 2 ³
3
4
Port 3
5
4
6
5
7
6
0
7
Port 1 ₆
7
Input/
Output
Data
Bus
Address Bus
A13-A8
Flash
Control Signals
Address Bus
A₇-A₀
EA# ALE /PSEN#
PROG#
1255 F07.0
FIGURE 4-1: I/O PIN ASSIGNMENTS FOR EXTERNAL HOST MODE
©2004 Silicon Storage Technology, Inc.
36
S71255-00-000
3/04