SST89E52RD2_06 Datasheet, PDF (11/81 Pages) Silicon Storage Technology, Inc – FlashFlex51 MCU

FlashFlex51 MCU
SST89E52RD2/RD / SST89E54RD2/RD / SST89E58RD2/RD
SST89V52RD2/RD / SST89V54RD2/RD / SST89V58RD2/RD
3.0 MEMORY ORGANIZATION
Data Sheet
The device has separate address spaces for program and
data memory.
3.1 Program Flash Memory
There are two internal flash memory blocks in the device.
The primary flash memory block (Block 0) has 8/16/32
KByte. The secondary flash memory block (Block 1) has 8
KByte. Since the total program address space is limited to
64 KByte, the SFCF[1:0] bit are used to control program
bank selection. Please refer to Figures 3-1 through 3-3 for
the program memory configuration. Program bank selec-
tion is described in the next section.
The 8K/16K/32K x8 primary SuperFlash block is organized
as 64/128/256 sectors, each sector consists of 128 Bytes.
The 8K x8 secondary SuperFlash block is organized as 64
sectors, each sector consists also of 128 Bytes.
For both blocks, the 7 least significant program address bits
select the byte within the sector. The remainder of the pro-
gram address bits select the sector within the block.
FFFFH
EA# = 0
EA# = 1
SFCF[1:0] = 00
FFFFH
E000H
DFFFH
8 KByte
Block 1
EA# = 1
SFCF[1:0] = 01
FFFFH
E000H
DFFFH
8 KByte
Block 1
EA# = 1
SFCF[1:0] = 10, 11
FFFFH
External
64 KByte
Not
Accessible
Not
Accessible
Not
Accessible
0000H
2000H
1FFFH
0000H
8 KByte
Block 1
2000H
1FFFH
0000H
8 KByte
Block 0
2000H
1FFFH
0000H
FIGURE 3-1: Program Memory Organization for 8 KByte SST89x52RDx
8 KByte
Block 0
1255 F01.1
©2006 Silicon Storage Technology, Inc.
11
S71255-05-000
5/06