SI5364-EVB Datasheet, PDF (4/14 Pages) Solid State Optronic – EVALUATION BOARD FOR Si5364 SONET/SDH PRECISION PORT CARD CLOCK IC

Si5364-EVB
Table 1. Si5364-EVB Assembly Rev B-01 Default Jumper/Switch Settings
Location
JP3
JP12
Signal
VSEL33
VDD33
State
1
Open
JP1
JP9
JP2
JP15
VALTIME
SMC/S3N
DSBLFOS
RVRT
AUTOSEL
DSBLFSYNC
MANCNTRL[0]
MANCNTRL[1]
FEC[0]
FEC[1]
BWSEL[0]
BWSEL[1]
FRQSEL_1[0]
FRQSEL_1[1]
FRQSEL_2[0]
FRQSEL_2[1]
FRQSEL_3[0]
FRQSEL_3[1]
FRQSEL_4[0]
FRQSEL_4[1]
FXD_DELAY
LED ENABLE_N
SYNCIN
FSYNC
0
1
0
1
1
0
0
1
0
0
1
1
1
1
1
1
1
1
1
1
0
ON
No Jumper
Installed
No Jumper
Installed
Notes
Si5364 device Internal Regulator enabled
Si5364 device VDD33 pins not connected to 2.5 V supply
plane
100 ms Validation Time
SONET Minimum Clock criteria selected
Frequency Offset alarms enabled
Revertive clock switching mode selected
Automatic input Selection enabled
FSYNC output enabled
CLKIN_A would be selected if AUTOSEL = 0
CLKIN_A would be selected if AUTOSEL = 0
FEC scaling factor = 1/1 (no FEC scaling)
FEC scaling factor = 1/1 (no FEC scaling)
Loop Bandwidth = 6400 Hz
Loop Bandwidth = 6400 Hz
CLKOUT_1 = 622 MHz Range
CLKOUT_1 = 622 MHz Range
CLKOUT_2 = 622 MHz Range
CLKOUT_2 = 622 MHz Range
CLKOUT_3 = 622 MHz Range
CLKOUT_3 = 622 MHz Range
CLKOUT_4 = 622 MHz Range
CLKOUT_4 = 622 MHz Range
Fixed Delay mode disabled
LED Status Indicators enabled
Header for SYNCIN input signal
Header for FSYNC output signal
4
Preliminary Rev. 0.33