SI5364-EVB Datasheet, PDF (2/14 Pages) Solid State Optronic – EVALUATION BOARD FOR Si5364 SONET/SDH PRECISION PORT CARD CLOCK IC

Si5364-EVB
Functional Description
The Si5364-EVB is the evaluation board for the Si5364
SONET/SDH Precision Port Card Clock IC. This
evaluation board provides access to all signals
associated with normal operation of the device. This
circuit board also is designed to provide access to signals
that are reserved for factory testing purposes.
Power Supply Selection and Connections
The Si5364-EVB board is switch selectable for
operation using either a single 3.3 V or a single 2.5 V
supply.
For operation using a 3.3 V supply, configure the board
as follows:
1. Remove power supply connections from the VDD and
GND terminals of the board’s power connector, J15.
2. Remove the connection between VDD33 and VDD25 by
removing the jumper on header JPI.
3. Set VSEL33 high by sliding the switch on the VSEL33
(JP3) to the side marked “1”.
4. Connect the power supply ground lead and 3.3 V supply
lead to the GND and VDD terminals of the board’s power
connector, J15.
For operation using a 2.5 V supply, configure the board
as follows:
1. Remove power supply connections from the VDD and
GND terminals of the board’s power connector, J15.
2. Set VSEL33 low by sliding the switch on the VSEL33 (JP3)
to the side marked “0”.
3. Connect VDD33 and VDD25 by installing a jumper
between one of the 3.3 V pins and one of the 2.5 V pins on
header JPI.
4. Connect the power supply ground lead and 2.5 V supply
lead to the GND and VDD terminals of the board’s power
connector, J15.
Power Consumption
Typical supply current draw for the Si5364-EVB with LED
indicators disabled and one clock output enabled is
120 mA. Each additional clock output that is enabled
adds approximately 15 mA. LED indicators, when
enabled, adds approximately 8 mA for each indicator that
is illuminated.
Si5364 Control Inputs
Most of the control inputs to the Si5364 are routed to the
center post of a SPDT switch located at JP1. The
switches are wired with the signal on the center pin,
VDD33 on one side pin, and GND on the other side pin.
Each input is easily configurable to a high or a low state.
There are three inputs to the Si5364 that are not routed to
switches at JP1. Two of these signals are INCDELAY and
DECDELAY. They are routed to push button switches
SW1 and SW2, respectively, through headers JP4 and
JP5. Inverters U6 and U7 condition the action of these
switches before being sent to the Si5364 device.
Pressing and releasing these switches provides a single
pulse to the control input for the Si5364. This is a
convenient method for evaluating the operation of the
INCDELAY and DECDELAY functions. Resistors R26
and R27 allow the user to disconnect the switches from
the device and drive the inputs from another source. JP4
and JP5 are not populated when shipped from the
factory. If an external source is required to drive the
INCDELAY and DECDELAY inputs, then populate these
two headers. This provides the user a convenient location
to connect the source.
Each LVTTL input on the Si5364 device has an internal
pull-down mechanism. The control inputs default to a low
state if no device drives the input.
RSTN/CAL Settings for Normal Operation
and Self-Calibration
The RSTN/CAL signal is an LVTTL input to the Si5364
and has an on-chip pull down mechanism. This pin must
be set high to enable normal operation of the Si5364
device.
Setting RSTN/CAL low forces the Si5364 into a reset
state. A low-to-high transition of RSTN/CAL enables the
part and initiates a self-calibration sequence.
The Si5364 device automatically initiates a self-
calibration at power-up if the RSTN/CAL signal is held
high. A self-calibration of the device also can be manually
initiated by pushing the RSTN/CAL switch, SW3, then
releasing. Self-calibration must be initiated manually after
changing the state of either the BWSEL[1:0] control
inputs or the FEC[1:0] inputs.
Whether manually initiated or automatically initiated at
power-up, the self-calibration process requires the
presence of a valid input clock. If the self-calibration is
initiated without a valid clock present, the device waits for
a valid clock before completing the self-calibration. The
Si5364 clock outputs drift to the lower end of the
operating frequency range as the device waits for a valid
clock. After the input clock is validated, the calibration
process runs to completion, the device locks to the input,
and the clock outputs shifts to their target frequencies.
Subsequent losses of the input clock do not require re-
calibration. If the clock input is lost after self-calibration,
the device enters Digital Hold mode. When the input
clock returns, the device re-locks to the input clock
without performing a self-calibration.
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Preliminary Rev. 0.33