SI5364-EVB Datasheet, PDF (3/14 Pages) Solid State Optronic – EVALUATION BOARD FOR Si5364 SONET/SDH PRECISION PORT CARD CLOCK IC

Si5364-EVB
Status Signals
The status outputs from the Si5364 device are each
routed to one pin of a two-row header, JP11. The header
is wired so that the signals are present on one side of the
header and a ground reference is present on the other.
The letter S marks the row of signal pins and the row of
ground pins is marked with the letter G.
On the Si5364-EVB board, the status outputs are also
routed to two buffer/driver ICs (U4 and U5) that drive one
LED indicator for each status signal.
Enabling and Disabling the Status Indicator
LEDs
The status LED driver outputs can be disabled. The
disabled driver outputs are placed into a high impedance
state to get a more accurate measurement of the current/
power being consumed by the Si5364 device. The LED
drivers are enabled when the switch at JP9 is switched to
ON. The driver outputs are disabled when the switch is
set to OFF.
Factory Test Headers
Locations for headers JP8 and JP10 are included on the
SI5364-EVB for factory testing. For customer evaluation,
these locations are not populated.
Differential Clock Input Signals
tantalum capacitor. This is the suggested compensation
circuit for Si5364 devices.
There are two considerations for selecting this
combination of compensation resistor and capacitor.
First, is the stability of the regulator. The second is noise
filtering.
The acceptable range for the time constant at this node
is 15 µs to 50 µs. The capacitor used on the board is a
33 µF capacitor with an ESR of .8 Ω. This yields a time
constant of 26.4 µs. The designer could decide to use a
330 µF capacitor with an ESR of .15 Ω. This yields a
time constant of 49.5 µs. Each of these cases provide a
compensation circuit that makes the output of the
regulator stable.
The second issue is noise filtering. For this, more
capacitance is usually better. For the two cases
described above, the 330 µF case provides greater
noise filtering. However, the large case size of the
330 µF capacitor might make it impractical for many
applications. The Si5364 device is specified with the
33 µF cap.
Default Jumper Settings
The default jumper settings for the Si5364-EVB board are
given in Table 1 on page 4. These settings configure the
board for operation from a 3.3 V supply.
The differential clock inputs to the Si5364-EVB are
terminated on the board at a location near the input SMA
connectors. The input SMA connectors are ac coupled to
the termination circuit. The termination circuit consists of
two 50 Ω resistors and a 0.1 µF capacitor, connected so
that the positive and negative inputs of the differential pair
each see a 50 Ω termination to "ac ground", and the line-
to-line termination impedance is 100 Ω. The signals are
then routed to the Si5364 device.
Single-ended operation is accomplished by supplying a
signal to one of the differential inputs, typically the
positive input. The other input should be shorted to
ground with an SMA shorting plug.
Differential Clock Output Signals
The differential clock outputs from the Si5364 device are
routed to the perimeter of the circuit board using 50 Ω
transmission structures. The capacitors that provide ac-
coupling are located near the clock output SMA
connectors.
Internal Regulator Compensation
The Si5364-EVB contains pad locations for a resistor
and a capacitor between the VDD25 node and ground.
The resistor pads are populated with a 0 Ω resistor. The
capacitor pads are populated with a low ESR 33 µF
Preliminary Rev. 0.33
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