W159B Datasheet, PDF (9/10 Pages) SpectraLinear Inc – Spread Spectrum System FTG for SMP Systems

W159B
CPUdiv2 Clock Outputs, CPUdiv2_0:1 (Lump Capacitance Test Load = 20 pF)
CPU = 133 MHz CPU = 100 MHz
Parameter
Description
Test Condition/Comments
Min. Typ. Max. Min. Typ. Max. Unit
t_P
Period
Measured on rising edge at 1.25V
15
15.3 20
20.4 ns
t_H
High Time
Duration of clock cycle above 2.0V
5.25
7.5
ns
t_L
Low Time
Duration of clock cycle below 0.4V
5.05
7.3
ns
t_R
Output Rise Edge Rate Measured from 0.4V to 2.0V
1
41
4 V/ns
t_F
Output Fall Edge Rate Measured from 2.0V to 0.4V
1
41
4 V/ns
t_D
Duty Cycle
Measured on rising and falling edge at 45
1.25V
55 45
55 %
t_JC
Jitter, Cycle-to-Cycle Measured on rising edge at 1.25V.
Maximum difference of cycle time
between two adjacent cycles.
250
250 ps
t_SK
Output Skew
Measured on rising edge at 1.25V
175
f_ST
Frequency Stabili-
Assumes full supply voltage reached
3
zation from Power-up within 1 ms from power-up. Short cycles
(cold start)
exist prior to frequency stabilization.
175 ps
3 ms
Z_o
AC Output Impedance Average value during switching
20
transition. Used for determining series
termination value.
20
:
APIC Clock Outputs, APIC0:2 (Lump Capacitance Test Load = 20 pF)
Parameter
Description
Test Condition/Comments
Min Typ Max
f
Frequency
Note 21
16.67
t_R
Output Rise Edge Rate Measured from 0.4V to 2.0V
1
4
t_F
Output Fall Edge Rate
Measured from 2.0V to 0.4V
1
4
t_D
Duty Cycle
Measured on rising and falling edge at 1.25V 45
55
f_ST
Frequency Stabilization Assumes full supply voltage reached within
3
from Power-up (cold start) 1 ms from power-up. Short cycles exist prior to
frequency stabilization.
Z_o
AC Output Impedance
Average value during switching transition. Used
20
for determining series termination value.
Note:
21. APIC clock is CPU/8 for CPU = 133 MHz and CPU/6 for CPU = 100 MHz.
Unit
MHz
V/ns
V/ns
%
ms
:
Rev 1.0, November 21, 2006
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