W159B Datasheet, PDF (1/10 Pages) SpectraLinear Inc – Spread Spectrum System FTG for SMP Systems

W159B
Spread Spectrum System FTG for SMP Systems
Features
• Maximized EMI suppression using Cypress’s spread
spectrum technology (0.5% down spread)
• Seven skew-controlled copies of CPU and 16.667-MHz
synchronous APIC output
• Two copies of fixed-frequency 33 MHz outputs
• Four copies of 66 MHz fixed-frequency outputs
• Two copies of CPU/2 outputs for synchronous memory
reference
• One copy of 48 MHz USB output
• Two copies of 14.31818 MHz reference clock
• Programmable to 133 or 100 MHz operation
• Power management control pins for clock stop and
shut down
• Available in 56-pin SSOP
Key Specifications
Supply Voltages: ......... V_DDQ3 = 3.3V±5%V_DDQ2 = 2.5V±5%
CPU Output Jitter: ...................................................... 200 ps
CPUdiv2, 3V33, APIC Output Jitter: ........................... 250 ps
CPU, 3V33 Output Edge Rate: .................................. >1 V/ns
48-MHz, 3V66, REF Output Jitter: .............................. 500 ps
CPU0:6, CPUdiv2_0:1 Output Skew: ......................... 175 ps
3V66, APIC0:6, 3V33 Output Skew: ........................... 250 ps
CPU to 3V66 Output Offset:.......... 0.0 to 1.5 ns (3V66 leads)
3V66 to 3V33 Output Offset:......... 1.5 to 3.0 ns (3V66 leads)
CPU to APIC Output Offset:.............1 to 3.0 ns (CPU Leads)
CPU to 3V33 Output Offsets:........1.0 to 4.0 ns (CPU Leads)
Logic inputs, except SEL133/100#, have 100-k: pull-up
resistors.
Table 1. Pin Selectable Frequency
SEL133/100#
CPU0:6 (MHz)
PCI
1
133 MHz
33.3 MHz
0
[11] 00 MHz
33.3 MHz
Block Diagram
X1
XTAL
X2
OSC
6W/4W#
SPREAD#
SEL133/100#
PLL 1
÷2
÷2/÷1.5
2
REF_[0:1]
5
CPU_[0:4]
2
CPU_[5:6]
2
CPUdiv2_[0:1]
4
3V66_[0:3]
PWRDWN#
FIXAPIC#
Power
Down
Logic
÷2
÷4
2
3V33_[0:1]
5
APIC_[0:4]
2
APIC_[5:6]
PLL2
1
48MHz
Pin Configuration
APIC2 1
GND 2
APIC1 3
APIC0 4
VDDQ2 5
X1 6
X2 7
VDDQ3 8
REF0/FIXAPIC#* 9
REF1/TEST#* 10
GND 11
VDDQ3 12
GND 13
48MHz 14
VDDQ3 15
3V66_0 16
3V66_1 17
VDDQ3 18
GND 19
3V66_2 20
3V66_3 21
VDDQ3 22
3V33_0 23
3V33_1 24
GND 25
6W/4W#* 26
VDDQ3 ²⁷
GND 28
56 APIC3
55 APIC4
54 VDDQ2
53 APIC5
52 APIC6
51 GND
50 SPREAD#*
49 VDDQ2
48 CPU0
47 CPU1
46 GND
45 GND
44 CPU2
43 CPU3
42 VDDQ2
41 VDDQ2
40 CPU4
39 CPU5
38 GND
37 GND
36 CPU6
35 VDDQ2
34 PWRDWN#*
33 GND
32 CPUdiv2_0
31 CPUdiv2_1
30 VDDQ2
29 SEL133/100#
Note:
1. Pins denoted by * have a 250-k: pull-up resistor. Design
should not rely solely on internal pull-up resistor to set I/O pins
HIGH.
Rev 1.0, November 21, 2006
2200 Laurelwood Road, Santa Clara, CA 95054
Tel:[phone] Fax:[phone]
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