W159B Datasheet, PDF (8/10 Pages) SpectraLinear Inc – Spread Spectrum System FTG for SMP Systems

W159B
48-MHZ Clock Output (Lump Capacitance Test Load = 20 pF)
Parameter
Description
Test Condition/Comments
f
Frequency, Actual
Determined by PLL divider ratio (see m/n below)
f_D
Deviation from 48 MHz
(48.008 – 48)/48
m/n
PLL Ratio
(14.31818 MHz x 57/17 = 48.008 MHz)
t_R
Output Rise Edge Rate Measured from 0.4V to 2.4V
t_F
Output Fall Edge Rate
Measured from 2.4V to 0.4V
t_D
Duty Cycle
Measured on rising and falling edge at 1.5V
f_ST
Frequency Stabilization Assumes full supply voltage reached within 1 ms
from Power-up (cold start) from power-up. Short cycles exist prior to
frequency stabilization.
Z_o
AC Output Impedance
Average value during switching transition. Used
for determining series termination value.
Min.
0.5
0.5
45
Typ.
48.008
+167
57/17
25
Max.
2
2
55
3
Unit
MHz
ppm
V/ns
V/ns
%
ms
:
2.5V AC Electrical Characteristics
T_A = 0°C to +70°C, V_DDQ3 = 3.3V±5%, V_DDQ2= 2.5V±5%
f_XTL = 14.31818 MHz
Spread Spectrum function turned off
AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the
clock output.^[20]
CPU Clock Outputs, CPU0:6 (Lump Capacitance Test Load = 20 pF)
CPU = 133 MHz CPU = 100 MHz
Parameter
Description
Test Condition/Comments
Min. Typ. Max. Min. Typ. Max. Unit
t_P
Period
Measured on rising edge at 1.25V
7.5
7.65 10
10.2 ns
t_H
High Time
Duration of clock cycle above 2.0V
1.87
3.0
ns
t_L
Low Time
Duration of clock cycle below 0.4V
1.67
2.8
ns
t_R
Output Rise Edge Rate Measured from 0.4V to 2.0V
1
41
4 V/ns
t_F
Output Fall Edge Rate Measured from 2.0V to 0.4V
1
41
4 V/ns
t_D
Duty Cycle
Measured on rising and falling edge at 45
1.25V
55 45
55 %
t_JC
Jitter, Cycle-to-Cycle Measured on rising edge at 1.25V.
Maximum difference of cycle time
between two adjacent cycles.
200
200 ps
t_SK
Output Skew
Measured on rising edge at 1.25V
175
175 ps
f_ST
Frequency Stabili-
Assumes full supply voltage reached
3
zation from Power-up within 1 ms from power-up. Short cycles
(cold start)
exist prior to frequency stabilization.
3 ms
Z_o
AC Output Impedance Average value during switching
20
transition. Used for determining series
termination value.
20
:
Note:
20. Period, Jitter, offset, and skew measured on rising edge at 1.25V.
Rev 1.0, November 21, 2006
Page 8 of 10