CY28312B-2 Datasheet, PDF (9/17 Pages) SpectraLinear Inc – FTG for VIA™ K7 Series Chipset with Programmable Output Frequency

CY28312B-2
Byte 13: Programmable Frequency Select N–Value Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
CPU_FSEL_N7
CPU_FSEL_N6
CPU_FSEL_N5
CPU_FSEL_N4
CPU_FSEL_N3
CPU_FSEL_N2
CPU_FSEL_N1
CPU_FSEL_N0
Default
0
0
0
0
0
0
0
0
Description
If Prog_Freq_EN is set, W300 will use the values programmed in
CPU_FSEL_N[7:0] and CPU_FSEL_M[6:0] to determine the CPU output
frequency. The new frequency will start to load whenever CPU_FSELM[6:0] is
updated.
The setting of FS_Override bit determines the frequency ratio for CPU,
SDRAM, AGP and SDRAM. When it is cleared, W312 will use the same
frequency ratio stated in the Latched FS[4:0] register. When it is set,
CY28312B-2 will use the frequency ratio stated in the SEL[4:0] register.
CY28312B-2 supports programmable CPU frequency ranging from 50 MHz to
248 MHz.
Byte 14: Programmable Frequency Select N–Value Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Pro_Freq_EN
CPU_FSEL_M6
CPU_FSEL_M5
CPU_FSEL_M4
CPU_FSEL_M3
CPU_FSEL_M2
CPU_FSEL_M1
CPU_FSEL_M0
Default
0
0
0
0
0
0
0
0
Description
Programmable output frequencies enabled
0 = disabled
1 = enabled
If Prog_Freq_EN is set, W300 will use the values programmed in
CPU_FSEL_N[7:0] and CPU_FSEL_M[6:0] to determine the CPU output
frequency. The new frequency will start to load whenever CPU_FSELM[6:0] is
updated.
The setting of FS_Override bit determines the frequency ratio for CPU,
SDRAM, AGP and SDRAM. When it is cleared, CY28312B-2 will use the same
frequency ratio stated in the Latched FS[4:0] register. When it is set,
CY28312B-2 will use the frequency ratio stated in the SEL[4:0] register.
CY28312B-2 supports programmable CPU frequency ranging from 50 MHz to
248 MHz.
Byte 15: Reserved Register
Bit
Pin#
Bit 7
–
Bit 6
–
Bit 5
–
Bit 4
–
Bit 3
–
Bit 2
–
Bit 1
–
Bit 0
–
Name
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Default
0
0
0
0
0
0
1
1
Description
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved. Write with ‘1’
Reserved. Write with ‘1’
Byte 16: Reserved Register
Bit
Bit 7
Bit 6
Bit 5
Pin#
–
–
–
Bit 4
–
Bit 3
–
Bit 2
–
Bit 1
–
Name
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Default
0
0
0
0
0
0
0
Description
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Rev 1.0, November 21, 2006
Page 9 of 17